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| 型號(hào)： | ICS1892Y |
| 英文描述： | 10Base-T/100Base-TX Integrated PHYceiver |
| 文件頁(yè)數(shù)： | 19/148頁(yè) |
| 文件大?。?/td> | 816K |
| 代理商： | ICS1892Y |
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Chapter 5
Operating Modes Overview
ICS1892, Rev. D, 2/26/01
February 26, 2001
19
ICS1892
2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
5.1.2
Specific Reset Operations
This section discusses the following specific ways that the ICS1892 can be reset:
Hardware reset (using the RESET* pin)
Power-on reset (applying power to the ICS1892)
Software reset (using Control Register bit 0.15)
Note:
At the completion of a reset (either hardware, power-on, or software), the ICS1892 sets all
registers to their default values.
5.1.2.1
Hardware Reset
Entering Hardware Reset
Holding the active-low RESET* pin low for a minimum of five REF_IN clock cycles initiates a hardware
reset (that is, the ICS1892 enters the reset state). During reset, the ICS1892 executes the steps listed in
Section 5.1.1.1, “Entering Reset”
.
Exiting Hardware Reset
After the signal on the RESET* pin transitions from a low to a high state, the ICS1892 completes in 640 ns
(that is, in 16 REF_IN clocks) steps 1 through 5, listed in
Section 5.1.1.2, “Exiting Reset”
. After the first five
steps are completed, the Serial Management Port is ready for normal operations, but this action does not
signify the end of the reset cycle. The reset cycle completes when the transmit clock (TXCLK) and receive
clock (RXCLK) are available, which is typically 53 ms after the RESET* pin goes high. [For details on this
transition, see
Section 10.5.17, “Reset: Hardware Reset and Power-Down”
.]
Note:
1.
2.
The MAC/Repeater Interface is not available for use until the TXCLK and RXCLK are valid.
The Control Register bit 0.15 does not represent the status of a hardware reset. It is a self-clearing bit
that is used to initiate a software reset.
5.1.2.2
Power-On Reset
Entering Power-On Reset
When power is applied to the ICS1892, it waits until the potential between V
DD
and V
SS
achieves a
minimum voltage of 4.5 VDC before entering reset and executing the steps listed in
Section 5.1.1.1,
“Entering Reset”
. After entering reset from a power-on condition, the ICS1892 remains in reset for
approximately 20
μ
s. (For details on this transition, see
Section 10.5.16, “Reset: Power-On Reset”
.)
Exiting Power-On Reset
The ICS1892 automatically exits reset and performs the same steps as for a hardware reset. (See
Section
5.1.1.2, “Exiting Reset”
.)
Note:
The only difference between a hardware reset and a power-on reset is that during a power-on
reset, the ICS1892 isolates the RESET* input pin. All other functionality is the same. As with a
hardware reset, the Control Register bit 0.15 does not represent the status of a power-on reset.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS1892Y-10 | 10Base-T/100Base-TX Integrated PHYceiver |
| ICS1892Y-14 | 10Base-T/100Base-TX Integrated PHYceiver |
| ICS1893AF | 3.3V 10Base-T/100Base-TX Integrated PHYceiverTM |
| ICS1893Y-10 | 3.3V 10Base-T/100Base-TX Integrated PHYceiverTM |
| ICS1893 | 3.3-V 10Base-T/100Base-TX Integrated PHYceiver⑩ |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS1892Y-10 | 制造商:ICS 制造商全稱:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver |
| ICS1892Y-14 | 制造商:ICS 制造商全稱:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver |
| ICS1893 | 制造商:ICS 制造商全稱:ICS 功能描述:3.3-V 10Base-T/100Base-TX Integrated PHYceiver |
| ICS1893_09 | 制造商:ICS 制造商全稱:ICS 功能描述:3.3-V 10Base-T/100Base-TX Integrated PHYceiver? |
| ICS1893AF | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
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