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| 型號(hào)： | ICS1892Y |
| 英文描述： | 10Base-T/100Base-TX Integrated PHYceiver |
| 文件頁(yè)數(shù)： | 32/148頁(yè) |
| 文件大?。?/td> | 816K |
| 代理商： | ICS1892Y |
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ICS1892, Rev. D, 2/26/01
February 26, 2001
32
Chapter 6
Interface Overviews
ICS1892 Data Sheet
2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
6.8
Configuration Interface
The Configuration and Status Interface pins (10/100SEL, 10/LP, ANSEL, DPXSEL, HW/SW, MII/SI,
NOD/REP, RESET* and RXTRI) allow the ICS1892 to be completely configured and controlled in
hardware. With these pins, the ICS1892 can accommodate the following:
10M or 100M operations
5 MAC/Repeater Interface configurations:
– 10M MII
– 100M MII
– 100M Symbol
– 10M Serial
– Link Pulse
Node or repeater applications
Full-duplex or half-duplex data links
In addition to the ISO/IEC-specified, MII control signals, the ICS1892 provides RXTRI, which is a tri-state
enable pin for the MII receive data path. When this pin is active (that is, a logic one), the pins RXCLK,
RXD[3:0], RXER, and RXDV are all tri-stated. Functionally, this pin affects the MII receive channel in the
same way as the Control Register’s isolate bit, bit 0.10. (The isolate bit also affects the transmit data path.)
The ICS1892 can tri-state these seven signals for all five types of MAC/Repeater Interface configurations,
not just the MII interface.
6.9
Status Interface
The ICS1892 LSTA pin provides a Link Status, and the LOCK pin provides a Stream Cipher Locking
Status. In addition, as listed in
Table 6-4
, the ICS1892 provides the five multiplexed pins that monitor the
data link by providing signals that drive LEDs. (
Table 9.2.2
lists the pin numbers.)
The ICS1892 multiplexes each of these five LED output signals with one of the five PHY address inputs.
The following example shows how this multiplexing takes place:
1.
The PHY Address bit P0 and the link activity LED (AC) share pin 58. During a reset of the ICS1892, the
signal on the link activity LED pin (as well as the other four LED pins) become inputs.
When the ICS1892 leaves the reset state, it latches the state of these inputs into the PHY Address bits
(that is, the Serial Management Port Address) described in
Table 8-16
.
Next, the ICS1892 converts these pin signals to output signals that can drive an LED directly as
follows: The state/value of each PHY Address bit is selected by connecting its associated LED signal
to either V
DD
(to select a logic one) or V
SS
(to select a logic zero).
After the reset process completes, the ICS1892 uses the latched PHY address to drive the LED,
independent of its connection to V
DD
or V
SS
.
2.
3.
4.
Table 6-4.
Pins for Monitoring the Data Link
Pin
LED Driven by the Pin’s Output Signal
P0AC
AC (Link
Ac
tivity) LED
P1CL
CL (
C
o
l
lisions) LED
P2LI
LI (
L
ink
I
ntegrity) LED
P3TD
TD (
T
ransmit
D
ata) LED
P4RD
RD (
R
eceive
D
ata) LED
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS1892Y-10 | 10Base-T/100Base-TX Integrated PHYceiver |
| ICS1892Y-14 | 10Base-T/100Base-TX Integrated PHYceiver |
| ICS1893AF | 3.3V 10Base-T/100Base-TX Integrated PHYceiverTM |
| ICS1893Y-10 | 3.3V 10Base-T/100Base-TX Integrated PHYceiverTM |
| ICS1893 | 3.3-V 10Base-T/100Base-TX Integrated PHYceiver⑩ |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS1892Y-10 | 制造商:ICS 制造商全稱:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver |
| ICS1892Y-14 | 制造商:ICS 制造商全稱:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver |
| ICS1893 | 制造商:ICS 制造商全稱:ICS 功能描述:3.3-V 10Base-T/100Base-TX Integrated PHYceiver |
| ICS1893_09 | 制造商:ICS 制造商全稱:ICS 功能描述:3.3-V 10Base-T/100Base-TX Integrated PHYceiver? |
| ICS1893AF | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 類(lèi)別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類(lèi)型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
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