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| 型號(hào)： | ICS1892Y |
| 英文描述： | 10Base-T/100Base-TX Integrated PHYceiver |
| 文件頁(yè)數(shù)： | 64/148頁(yè) |
| 文件大?。?/td> | 816K |
| 代理商： | ICS1892Y |
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ICS1892, Rev. D, 2/26/01
February 26, 2001
64
Chapter 8
Management Register Set
ICS1892 Data Sheet
2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
8.2.5
Low Power Mode (bit 0.11)
This bit provides one way to control the ICS1892 low-power mode function. When bit 0.11 is logic:
Zero, there is no impact to ICS1892 operations.
One, the ICS1892 enters the low-power mode. In this case, the ICS1892 disables all internal functions
and drives all MAC/repeater output pins low except for those that support the MII Serial Management
Port.
Note:
There are two ways the ICS1892 can enter low-power mode. When entering low-power mode:
By setting bit 0.11 to logic one, the ICS1892 maintains the value of all management register bits
except the latching high (LH) and latching low (LL) status bits, which are re-initialized to their
default values instead. (For more information on latching high and latching low bits, see
Section
8.1.4.1, “Latching High Bits”
and
Section 8.1.4.2, “Latching Low Bits”
.)
During a reset, the ICS1892 sets all management register bits to their default values.
8.2.6
Isolate (bit 0.10)
This bit controls the ICS1892 Isolate function. When bit 0.10 is logic:
Zero, there is no impact to ICS1892 operations.
One, the ICS1892 electrically isolates its data paths from the MAC/Repeater Interface. The ICS1892
places all MAC/repeater output signals, (TXCLK, RXCLK, RXDV, RXER, RXD[3:0], COL, and CRS), in a
high-impedance state and it isolates all MAC/repeater input signals, (TXD[3:0], TXEN, and TXER). In
this mode, the Management Interface continues to operate normally (that is, bit 0.10 does not affect the
Management Interface).
The default value for bit 0.10 depends upon the PHY address of
Table 8-16
. If the PHY address:
Is equal to 00000b, then the default value of bit 0.10 is logic one, and the ICS1892 isolates itself from the
MAC/Repeater Interface.
Is not equal to 00000b, then the default value of bit 0.10 is logic zero, and the ICS1892 does not isolate
its MAC/Repeater Interface.
8.2.7
Restart Auto-Negotiation (bit 0.9)
This bit allows an STA to restart the auto-negotiation process in Software mode (that is, the HW/SW pin is
logic one). When bit 0.12 is logic:
Zero, the Auto-Negotiation sublayer is disabled, and the ICS1892 isolates any attempt by the STA to set
bit 0.9 to logic one.
One (as set by an STA), the ICS1892 restarts the auto-negotiation process. Once the auto-negotiation
process begins, the ICS1892 automatically sets this bit to logic zero, thereby providing the self-clearing
feature.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS1892Y-10 | 10Base-T/100Base-TX Integrated PHYceiver |
| ICS1892Y-14 | 10Base-T/100Base-TX Integrated PHYceiver |
| ICS1893AF | 3.3V 10Base-T/100Base-TX Integrated PHYceiverTM |
| ICS1893Y-10 | 3.3V 10Base-T/100Base-TX Integrated PHYceiverTM |
| ICS1893 | 3.3-V 10Base-T/100Base-TX Integrated PHYceiver⑩ |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS1892Y-10 | 制造商:ICS 制造商全稱:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver |
| ICS1892Y-14 | 制造商:ICS 制造商全稱:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver |
| ICS1893 | 制造商:ICS 制造商全稱:ICS 功能描述:3.3-V 10Base-T/100Base-TX Integrated PHYceiver |
| ICS1893_09 | 制造商:ICS 制造商全稱:ICS 功能描述:3.3-V 10Base-T/100Base-TX Integrated PHYceiver? |
| ICS1893AF | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
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