- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄360744 > ICS1892Y 10Base-T/100Base-TX Integrated PHYceiver PDF資料下載
參數(shù)資料
| 型號(hào)： | ICS1892Y |
| 英文描述： | 10Base-T/100Base-TX Integrated PHYceiver |
| 文件頁(yè)數(shù)： | 68/148頁(yè) |
| 文件大?。?/td> | 816K |
| 代理商： | ICS1892Y |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)當(dāng)前第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)
ICS1892, Rev. D, 2/26/01
February 26, 2001
68
Chapter 8
Management Register Set
ICS1892 Data Sheet
2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
8.3.6
IEEE Reserved Bits (bits 1.10:7)
The IEEE reserves these bits for future use. When an STA:
Reads a reserved bit, the ICS1892 returns a logic zero.
Writes a reserved bit, the STA must use the default value specified in this data sheet.
Both the ISO/IEC standard and the ICS1892 reserve the use of some Management Register bits. ICS uses
some of these reserved bits to invoke ICS1892 test functions. To ensure proper operation of the ICS1892,
an STA must maintain the default value of these bits. Therefore, ICS recommends that an STA write the
default value to all reserved bits during all Management Register write operations.
Reserved bits 1.10:7 are Command Override Write (CW) bits. When bit 16.15, the Command Register
Override bit is logic:
Zero, the ICS1892 isolates all STA writes to CW bits.
One, an STA can modify the value of these bits.
8.3.7
MF Preamble Suppression (bit 1.6)
Status Register bit 1.6 is the Management Frame (MF) Preamble Suppression bit. The ICS1892 sets bit 1.6
to inform the STA of its ability to receive frames that do not have a preamble. When this bit is logic:
Zero, the ICS1892 is indicating it cannot accept frames with a suppressed preamble.
One, the ICS1892 is indicating it can accept frames that do not have a preamble.
Although the ICS1892 supports Management Frame Preamble Suppression, its default value for bit 1.6 is
logic zero. This default value ensures that bit 1.6 is backward compatible with the ICS 1890, which does not
have this capability. As the means of enabling this feature, bit 1.6 of the ICS1892 is a Command Override
Write bit, instead of a Read-Only bit as in the ICS 1890. An STA uses the bit 1.6 to enable MF Preamble
Suppression in the ICS1892. [See the description of bit 16.15, the Command Override Write Enable bit, in
Section 8.11, “Register 16: Extended Control Register”
.]
8.3.8
Auto-Negotiation Complete (bit 1.5)
An STA reads bit 1.5 to determine the state of the ICS1892 auto-negotiation process. The ICS1892 sets the
value of this bit using two criteria. When its Auto-Negotiation sublayer is:
Disabled, the ICS1892 sets bit 1.5 to logic zero.
Enabled, the ICS1892 sets bit 1.5 to a value based on the state of the Auto-Negotiation State Machine.
When the Auto-Negotiation State Machine is enabled, it sets bit 1.5 to logic one only upon completion of
the auto-negotiation process. This setting indicates to the STA that a link is arbitrated and the contents of
Management Registers 4, 5 and 6 are valid. For more detailed information regarding the
auto-negotiation process, see
Section 7.2, “Functional Block: Auto-Negotiation”
.
Bit 1.5 is a latching high (LH) bit. (For more information on latching high and latching low bits, see
Section
8.1.4.1, “Latching High Bits”
and
Section 8.1.4.2, “Latching Low Bits”
.)
Note:
An Auto-Negotiation Restart does not clear an LH bit.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS1892Y-10 | 10Base-T/100Base-TX Integrated PHYceiver |
| ICS1892Y-14 | 10Base-T/100Base-TX Integrated PHYceiver |
| ICS1893AF | 3.3V 10Base-T/100Base-TX Integrated PHYceiverTM |
| ICS1893Y-10 | 3.3V 10Base-T/100Base-TX Integrated PHYceiverTM |
| ICS1893 | 3.3-V 10Base-T/100Base-TX Integrated PHYceiver⑩ |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS1892Y-10 | 制造商:ICS 制造商全稱(chēng):ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver |
| ICS1892Y-14 | 制造商:ICS 制造商全稱(chēng):ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver |
| ICS1893 | 制造商:ICS 制造商全稱(chēng):ICS 功能描述:3.3-V 10Base-T/100Base-TX Integrated PHYceiver |
| ICS1893_09 | 制造商:ICS 制造商全稱(chēng):ICS 功能描述:3.3-V 10Base-T/100Base-TX Integrated PHYceiver? |
| ICS1893AF | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 類(lèi)別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類(lèi)型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。