參數(shù)資料
型號(hào)： IDT77155L155PX
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 數(shù)字傳輸電路
英文描述： PHY (TC-PMD) USER NETWORK INTERFACE FOR 155 MBPS ATM NETWORK APPLICATIONS
中文描述： ATM NETWORK INTERFACE, PQFP128
封裝： 20 X 14 MM, PLASTIC, QFP-128
文件頁(yè)數(shù)： 20/50頁(yè)
文件大?。?/td> 307K
代理商： IDT77155L155PX
8.03
20
IDT77155
155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE
ADVANCED INFORMATION
Commercial Temperature Range
INTERRUPT REGISTER
ADDRESS 0X02
DEFAULT = 8’BXXXXXXXX
Bit
Bit 7
Type
R
Symbol
txOOLInt
Function
Transmit reference out of lock interrupt status indication. It indicates the
transmit clock synthesis PLL is unable to lock to the reference frequency
TRCLK+/-. This bit is cleared when the register is read.
Asserted when the loss of cell delineation (LOC) signal changes state.
This bit is reset after a read to this register.
Receive data out of lock interrupt status indication. It indicates the receive
clock/data recovery PLL’s recovered clock is not within Bellcore’s
requirement of frequency variation with respect to the reference clock
RRCLK+/-. It is also asserted if no transitions have occurred on the
RXD+/- inputs for 80 bit periods. This bit is cleared when the register is
read.
Interrupt is asserted upon the detection of an interrupt from the tx cell
delineation block.
Interrupt is asserted upon the detection of an interrupt from the rx cell
delineation block.
Interrupt is asserted upon the detection of an interrupt from the rx path
overhead section of the transmission convergence block.
Interrupt is asserted upon the detection of an interrupt from the rx line
overhead section of the transmission convergence block.
Interrupt is asserted upon the detection of an interrupt from the rx section
overhead section of the transmission convergence block.
Bit 6
R
rxLOCInt
Bit 5
R
rxOOLInt
Bit 4
R
txCDi
Bit 3
R
rxCDi
Bit 2
R
rxPOHi
Bit 1
R
rxLOHi
Bit 0
R
rxSOHi
MASTER CLOCK MONITOR REGISTER
ADDRESS 0X04
DEFAULT = 8’BXXXXXXXX
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Type
—
—
—
—
R
Symbol
—
—
—
—
rrclkReg
Function
Reserved
Reserved
Reserved
Reserved
RRCLK+/- monitor. Set on the rising edge of RRCLK+/-. Cleared when
this register is read.
TRCLK+/- monitor. Set on the rising edge of TRCLK+/-. Cleared when
this register is read.
RCLK monitor. Set on the rising edge of the output clock RCLK. Cleared
when this register is read.
TCLK monitor. Set on the rising edge of the output clock TCLK. Cleared
when this register is read.
Bit 2
R
trclkReg
Bit 1
R
rclkReg
Bit 0
R
tclkReg
相關(guān)PDF資料
PDF描述
IDT77301 UTOPIAFIFO 1 TO 4 (128 x 9 x 4) DEMULTIPLEXER-FIFO
IDT77301L12PF UTOPIAFIFO 1 TO 4 (128 x 9 x 4) DEMULTIPLEXER-FIFO
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IDT77305 UTOPIAFIFO 4 PORT MULTIPLEXER FIFO
IDT77911 Octal Transceivers And Line/MOS Drivers With 3-State Outputs 20-PDIP -40 to 85
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