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參數(shù)資料
| 型號(hào)： | IDT77155L155PX |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | PHY (TC-PMD) USER NETWORK INTERFACE FOR 155 MBPS ATM NETWORK APPLICATIONS |
| 中文描述： | ATM NETWORK INTERFACE, PQFP128 |
| 封裝： | 20 X 14 MM, PLASTIC, QFP-128 |
| 文件頁數(shù)： | 36/50頁 |
| 文件大?。?/td> | 307K |
| 代理商： | IDT77155L155PX |
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8.03
36
IDT77155
155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE
ADVANCED INFORMATION
Commercial Temperature Range
ADDRESS 0X58
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
—
—
—
—
—
R
R
R
Symbol
—
—
—
—
—
cellCnt[18]
cellCnt[17]
cellCnt[16]
Function
Reserved
Reserved
Reserved
Reserved
Reserved
Receive cell counter bit
Receive cell counter bit
Receive cell counter bit
NOTE:
1.cellCnt [18:0] Receive cell counter of the number of cells passed thru’ to the ATM. Cells filtered due to HEC errors or idle/unassigned cells are not counted.
This is a cumulative counter keeping track of rx cells from the previous poll of these registers. The count is polled by writing to either of these registers
(‘h56, ‘h57, or ‘h58), the HEC error registers, or to address ‘h00. Such a write transfers accumulated errors to a holding register which may be read later,
and the registers are cleared. This transfer and reset of the registers are done such that coincident events are not lost. All error/count registers in the receive
sections of the transmission convergence block or the cell delineation block may be polled by a write to the master register ‘h00.
RECEIVE CELL CONFIGURATION REGISTER
ADDRESS 0X59
DEFAULT = 8’B11111100
Bit
Bit 7
Type
R/W
Symbol
GFCen[3]
Function
GFC enable bits. This determines which GFC bits are presented on the
RGFC output. If a GFCen bit is a logic one, the RGFC output presents
appropriate bit location the state of the associated GFC bit in the
current cell.
Bit 6
Bit 5
Bit 4
Bit 3
R/W
R/W
R/W
R/W
GFCen[2]
GFCen[1]
GFCen[0]
FixSen
Fixed stuff column control for STS-1 mode. When asserted high, the column
30 and 59 of the received SPE are assigned as fixed stuff columns. If FixSen is
low, Column 30 and 59 are assigned as ATM payload columns.
RCA level control. When asserted to a logic one, a high to low transition on
RCA indicates the receive FIFO is empty. When a logic zero, a high to low
transition on RCA indicates the receive FIFO in almost empty and contains
only 4 more bytes to be read.
HEC filter bits. It indicates the number of consecutive error free cells
required in the detection mode before reverting back to the correction
mode, of the HEC verification state machine.
HECfltr[1:0]
Cell acceptance threshold
00
one ATM cell with correct HEC to revert to the
connection mode. This cell is accepted.
01
two ATM cells with correct HEC to revert to the
correction mode. The last cell is accepted
10
four ATM cells with correct HEC to revert to the
correction mode. The last cell is accepted
11
eight ATM cells with correct HEC to revert to the
correction mode. The last cell is accepted
Bit 2
R/W
RCA level
Bit 1
R/W
HECftr[1]
Bit 0
R/W
HECftr[0]
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