參數(shù)資料
型號(hào)： IDT77155L155PX
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 數(shù)字傳輸電路
英文描述： PHY (TC-PMD) USER NETWORK INTERFACE FOR 155 MBPS ATM NETWORK APPLICATIONS
中文描述： ATM NETWORK INTERFACE, PQFP128
封裝： 20 X 14 MM, PLASTIC, QFP-128
文件頁(yè)數(shù)： 37/50頁(yè)
文件大?。?/td> 307K
代理商： IDT77155L155PX
IIDT77155
155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE
ADVANCED INFORMATION
Commercial Temperature Range
8.03
37
RECEIVE ID ADDRESS REGISTER
ADDRESS 0X5A
DEFAULT = 8’B00000000
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Type
—
—
—
—
—
—
R/W
Symbol
—
—
—
—
—
—
IDAddr[1]
Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Device ID value for the receive portion of the receive UTOPIA logic. In
multi-PY mode, the appropriate receive UTOPIA signals are driven as
per UTOPIA level 2 protocol when the RXADDR bus value matches the
value in this register. This has no effect in single-PHY mode.
Bit 0
R/W
IDAddr[0]
TRANSMIT CELL CONTROL REGISTER
ADDRESS 0X60
DEFAULT = 8’B00000100
Bit
Bit 7
Type
R/W
Symbol
fovrIEn
Function
Transmit FIFO overrun interrupt enable. Enables the generation of an
interrupt due to a FIFO overrun or when the TSOC input is sampled high
during any position other than the first byte.
Start of cell interrupt. This bit is set high when the TSOC input is sampled high
during any position other than the first byte. When such a condition occurs, the
cell delineation logic assumes the new SOC signal is the start of a new cell,
and the previous few bytes are discarded.
Thus, cell delineation is performed in the transmit direction also. This bit is
cleared after a read of this register.
Transmit FIFO overrun interrupt. This bit is cleared after a read to this
register.
Invert the HEC bytes before transmission for diagnostic purposes
when this bit is set to a logic one.
Disables the generation & insertion of the of the header error check
sequence.
Controls the addition of the coset polynomial. When a logic one, the coset
polynomial is added to the header prior to transmission.
Controls the descrambling of the cell payload. When asserted high,
payload scrambling is disabled.
Reset tx FIFO. Used to reset the four cell transmit FIFO when asserted
to a logic one. The FIFO ignores all writes until this bit is cleared.
Bit 6
R
socInt
Bit 5
R
fovrInt
Bit 4
R/W
HECInv
Bit 3
R/W
HECdis
Bit 2
R/W
csetAdd
Bit 1
R/W
scrDis
Bit 0
R/W
txFIFOrst
相關(guān)PDF資料
PDF描述
IDT77301 UTOPIAFIFO 1 TO 4 (128 x 9 x 4) DEMULTIPLEXER-FIFO
IDT77301L12PF UTOPIAFIFO 1 TO 4 (128 x 9 x 4) DEMULTIPLEXER-FIFO
IDT77301L12PFI UTOPIAFIFO 1 TO 4 (128 x 9 x 4) DEMULTIPLEXER-FIFO
IDT77305 UTOPIAFIFO 4 PORT MULTIPLEXER FIFO
IDT77911 Octal Transceivers And Line/MOS Drivers With 3-State Outputs 20-PDIP -40 to 85
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