參數(shù)資料
型號(hào)： IDT77155L155PX
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 數(shù)字傳輸電路
英文描述： PHY (TC-PMD) USER NETWORK INTERFACE FOR 155 MBPS ATM NETWORK APPLICATIONS
中文描述： ATM NETWORK INTERFACE, PQFP128
封裝： 20 X 14 MM, PLASTIC, QFP-128
文件頁(yè)數(shù)： 8/50頁(yè)
文件大?。?/td> 307K
代理商： IDT77155L155PX
8.03
8
IDT77155
155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE
ADVANCED INFORMATION
Commercial Temperature Range
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Rating
V
TERM
Terminal Voltage
with respect to DVGND
T
A
Operating
Temperature
T
BIAS
Temperature Under
Bias
T
STG
Storage
Temperature
I
OUT
DC Output Current
Commercial
–0.5 to +7.0
Unit
V
0 to +70
°
C
–55 to +125
°
C
–55 to +125
°
C
50
mA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliabilty.
3139 tbl 02
Symbol
C
IN
(1)
Parameter
Conditions
Max.
Unit
Input
Capacitance
Output
Capacitance
VIN = 0V
10
pF
C
OUT
(1)
VOUT = 0V
10
pF
CAPACITANCE
(TA = +25
°
C)
NOTE:
1. Characterized values, not currently tested.
3139 tbl 05
Notes
1. All inputs operate at TTL levels except the PECL inputs.
2. RDAT[7:0], RXPRTY, RCP, RGFC, RSOC, TCA, TCLK, RCLK, TCP outputs have an 8 ma drive capability, while all other digital outputs have 4 ms drive.
3. All analog power/ground pins should be isolated from the digital power/ground pins, preferably with separate power supplies. It is recommanded to have
separate ground planes on the board also.
Symbol
TXGND
Name
Ground
I/O
G
Description
Ground pin for TXC+/- and TXD+/- outputs. Should be physically isolated from the other
ground analog pins.
Pin #: 17
Core and pad ring power connected to a decoupled 5V dc
Pin #: 18, 20, 55, 61, 73, 81, 107, 114
VCLK is used as a test mode input to the chip. It should be asserted only when testing the
chip on a tester. It shortens the count values for most receive error counters to enable the
testing to be done in a reasonable amount of time. VCLK has an intergral pull-down registor.
Pin #: 99
Active low write signal to update registers. The data bus contents are latched into the
addressed register on the rising edge of the write signal when the chip select (CS) is
asserted.
Pin #: 104
Transmit off signal prevents the insertion of cells from the transmit FIFO into the transmit
frames. If asserted, idle/unassigned cells only are transmitted irrespective of the state of the
transmit FIFO. XOFF is an asynchronous signal and has an integral pull-down registor.
Pin #: 50
Vcc
Power
P
VCLK
Vector Clock
I
WR
Write
I
XOFF
Transmit Off
I
PIN DESCRIPTIONS (CONTINUED)
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