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參數(shù)資料
| 型號： | IDT77155L155PX |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | PHY (TC-PMD) USER NETWORK INTERFACE FOR 155 MBPS ATM NETWORK APPLICATIONS |
| 中文描述： | ATM NETWORK INTERFACE, PQFP128 |
| 封裝： | 20 X 14 MM, PLASTIC, QFP-128 |
| 文件頁數(shù)： | 6/50頁 |
| 文件大?。?/td> | 307K |
| 代理商： | IDT77155L155PX |
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8.03
6
IDT77155
155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE
ADVANCED INFORMATION
Commercial Temperature Range
Symbol
RSOC
Name
Receive Start
of Cell
I/O
O
Description
Indication to the ATM layer. This is asserted during the first byte of each tristate cell and is
updated on the rising edge of RFCLK. RSOC is tristated if TSEN is asserted or if MPHYEN is
asserted. In UTOPIA single-phy mode, it is driven if RRDENB is asserted (TSEN also
asserted) or always driven if TSEN is low. In UTOPIA multi-phy mode, RSOC is driven
following the level-2 protocol.
Pin #: 83
Active low asynchronous reset from the system. RST has integral pull-up resistor. RST need
not be asserted to reset the chip.
Pin #: 101
Receive address indicates the ID of the device which should respond to the receive bus
signals in UTOPIA level-2 multi-phy mode (when MPHYEN is asserted). It indicates the
device which should drive the receive cell to ATM device. The device ID may be programmed
in a receive ID register. The device ID register contain a default address of 0. RXADDR[1:0]
is sampled on the rising edge of RFCLK. RXADDR[1:0] inputs have integral pull-up resistors.
RXADDR[1:0] inputs are ignored when MPHYEN is not asserted.
Pin #: RXADDR0/46, RXADDR1/45
NRZ encoded receive differential data inputs which contain STS-3c or STS-1 data, and
sampled on the rising edge of RRCLK+/- if RBYP asserted, else the receive clock are
recovered from the data stream.
Pin #: RXD+/26, RXD-/25
Sliced versions of the RXD+/- inputs, to allow decision feedback equalization (DFE) to
correct baseline wander. These outputs could be programmed to be pure PECL. Defaults is a
rail-to-rail swing.
Pin #: RXDO+/22, RXDO-/25
Indicates the parity of the RDAT[7:0] bus. Odd or even parity may be selected. Tristate
RXPRTY is enabled on the rising edge of RFCLK, RXPRTY is tristate if TSEN is asserted or
if MPHYEN is asserted. In UTOPIA single-phy mode, it is driven if RRDENB is asserted
(TSEN also asserted) or always driven if TSEN is low. In UTOPIA multi-phy mode, RXPRTY
is driven following the level-2 protocol.
Pin #: 82
Active high transmit bypass input disables clock generator. If enabled, the clock inputs
TRCLK+/- become the transmit line lock at 155.52 MHz or 51.84 MHz. If disabled, the
transmit clock is synthesized from a 19.44 MHz or 6.48 MHz reference clock on
TRCLK+/-. TBYP has an integral pull down resistor.
Pin #: 2
Signal indicates the availability of a complete cell space in the transmit FIFO. This signal
when asserted indicates a maximum of 4 more transmit data writes will be accepted or that
the transmit FIFO is full and no more writes will be accepted. The indication of the transmit
FIFO level is programmable, as is the polarity of this signal. The FIFO depth at which the
TCA signal indicates the unavailability of data space in the FIFO may be set to one, two,
three, or four cells. TCA is updated on the rising edge of TFCLK.
Pin #: 86
The transmit byte clock provides a timing reference, and is a divide-by-8 version of the
synthesized clock when TBYP is disabled or TRCLK+/- when TBYP is enabled.
Pin #: 54
Transmit GFC cell pulse indicates the expected place of the transmit GFC bits. TCP is
updated on the rising edge of TCLK.
Pin #: 51
The transmit cell data from the ATM layer sampled on the rising edge of TFCLK. It carries
the 53 cell bytes. It is considered valid only when the TWRENB signal is asserted.
Pin #: TDAT0/87, TDAT1/88, TDAT2/89, TDAT3/90. TDAT4/91, TDAT5/92, TDAT6/93.
TDAT7/94
The transmit ATM clock from the ATM layer <= 40 MHz. The start of cell indication, the
transmit data, the transmit data parity, and the enable signals are sampled on the rising edge
of this clock.
Pin #: 84
RST
Reset
I
RXADDR[0]
RXADDR[1]
Receive Address
I
RXD+
RXD-
Receive
Differential
Data Inputs
I
RXDO+
RXDO-
Receive
Differential
Data Outputs
O
RXPRTY
Receive Parity
O
TBYP
Transmit Bypass
I
TCA/
TXFULL
Transmit Cell
Available
O
TCLK
Transmit Clock
O
TCP
Transmit Cell
Pulse
O
TDAT[0]-
TDAT[7]
Transmit Cell
Data
I
TFCLK
Transmit FIFO
Clock
I
PIN DESCRIPTIONS (CONTINUED)
相關(guān)PDF資料 |
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|---|---|
| IDT77301 | UTOPIAFIFO 1 TO 4 (128 x 9 x 4) DEMULTIPLEXER-FIFO |
| IDT77301L12PF | UTOPIAFIFO 1 TO 4 (128 x 9 x 4) DEMULTIPLEXER-FIFO |
| IDT77301L12PFI | UTOPIAFIFO 1 TO 4 (128 x 9 x 4) DEMULTIPLEXER-FIFO |
| IDT77305 | UTOPIAFIFO 4 PORT MULTIPLEXER FIFO |
| IDT77911 | Octal Transceivers And Line/MOS Drivers With 3-State Outputs 20-PDIP -40 to 85 |
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