參數(shù)資料
型號： IDT77155L155PX
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 數(shù)字傳輸電路
英文描述： PHY (TC-PMD) USER NETWORK INTERFACE FOR 155 MBPS ATM NETWORK APPLICATIONS
中文描述： ATM NETWORK INTERFACE, PQFP128
封裝： 20 X 14 MM, PLASTIC, QFP-128
文件頁數(shù)： 28/50頁
文件大?。?/td> 307K
代理商： IDT77155L155PX
8.03
28
IDT77155
155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE
ADVANCED INFORMATION
Commercial Temperature Range
RECEIVE PATH SIGNAL LABEL BYTE REGISTER
DEFAULT = 8’BXXXXXXXX
ADDRESS 0X37
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Symbol
C2rx[7]
C2rx[6]
C2rx[5]
C2rx[4]
C2rx[3]
C2rx[2]
C2rx[1]
C2rx[0]
Function
Receive C2 Bit 7
Receive C2 Bit 6
Receive C2 Bit 5
Receive C2 Bit 4
Receive C2 Bit 3
Receive C2 Bit 2
Receive C2 Bit 1
Receive C2 Bit 0
NOTE:
1. C2rx[7:0] most recent errored path label byte received which led to the C2
interrupt.
RECEIVE PATH OVERHEAD BIP ERROR COUNTER
DEFAULT = 16’HXXXX
ADDRESS 0X38
Bit
Bit 7
Bit 6
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
Symbol
B3ErrCnt[7]
B3ErrCnt[5]
B3ErrCnt[4]
B3ErrCnt[3]
B3ErrCnt[2]
B3ErrCnt[1]
B3ErrCnt[0]
Function
B3 error counter bit
B3 error counter bit
B3 error counter bit
B3 error counter bit
B3 error counter bit
B3 error counter bit
B3 error counter bit
ADDRESS 0X39
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Symbol
B3ErrCnt[15]
B3ErrCnt[14]
B3ErrCnt[13]
B3ErrCnt[12]
B3ErrCnt[11]
B3ErrCnt[10]
B3ErrCnt[9]
B3ErrCnt[8]
Function
B3 error counter bit
B3 error counter bit
B3 error counter bit
B3 error counter bit
B3 error counter bit
B3 error counter bit
B3 error counter bit
B3 error counter bit
NOTE:
1. B3ErrCnt Receive path overhead BIP (B3) error counter. Cumulative
error counter keeping track of errors from the previous poll of these
registers. The error count is polled by writing to either of the registers, or
either of the RDI error registers, or to address ‘h00. Such a write transfers
accumulated errors to a holding register which may be read later, and the
registers are cleared. This transfer and reset of the registers are done
such that coincident events are not lost. All error registers in the receive
sections of the transmission convergence block or the cell delineation
block may be polled by a write to the master register ‘h00
RECEIVE PATH FEBE COUNTER
DEFAULT = 16’HXXXX
ADDRESS 0X3A
Bit
Bit 7
Bit 6
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
Symbol
PFEBECnt[7]
PFEBECnt[5]
PFEBECnt[4]
PFEBECnt[3]
PFEBECnt[2]
PFEBECnt[1]
PFEBECnt[0]
Function
Path FEBE counter bit
Path FEBE counter bit
Path FEBE counter bit
Path FEBE counter bit
Path FEBE counter bit
Path FEBE counter bit
Path FEBE counter bit
ADDRESS 0X3B
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Symbol
PFEBECnt[15]
PFEBECnt[14]
PFEBECnt[13]
PFEBECnt[12]
PFEBECnt[11]
PFEBECnt[10]
PFEBECnt[9]
PFEBECnt[8]
Function
Path FEBE counter bit
Path FEBE counter bit
Path FEBE counter bit
Path FEBE counter bit
Path FEBE counter bit
Path FEBE counter bit
Path FEBE counter bit
Path FEBE counter bit
NOTE:
1. PFEBECnt[15:0] Receive path FEBE (Bit 1-4 of G1 byte) counter. Cumu-
lative error counter keeping track of errors from the previous poll of these
registers. The error count is polled by writing to either of the registers, or
either of the BIP (B3) error registers, or to address ‘h00. Such a write
transfers accumulated errors to a holding register which may be read later,
and the registers are cleared. This transfer and reset of the registers are
done such that coincident events are not lost. All error registers in the
receive sections of the transmission convergence block or the cell
delineation block may be polled by a write to the master register‘h00.
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