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參數(shù)資料
| 型號： | IDT77155L155PX |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | PHY (TC-PMD) USER NETWORK INTERFACE FOR 155 MBPS ATM NETWORK APPLICATIONS |
| 中文描述： | ATM NETWORK INTERFACE, PQFP128 |
| 封裝： | 20 X 14 MM, PLASTIC, QFP-128 |
| 文件頁數(shù)： | 33/50頁 |
| 文件大?。?/td> | 307K |
| 代理商： | IDT77155L155PX |
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IIDT77155
155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE
ADVANCED INFORMATION
Commercial Temperature Range
8.03
33
RECEIVE CELL CONTROL REGISTER
ADDRESS 0X50
DEFAULT = 8’B00000100
Bit
Bit 7
Type
R
Symbol
OCD
Function
Out of cell delineation status indication. When asserted high, the cell
delineation state machine is in the hunt or presync state.
Select odd or even parity for RXPRTY output. When set to logic one, it is
even parity over the outputs RDAT[7:0], else it is odd parity.
When enabled, filtering of cells with matching the pattern in cell header
register ‘h52 masked with the mask register ‘h53 is disabled. Filtering of field
with VPI = VCI = 0 is ignored and all cells are passed to the ATM layer.
Disables the HEC error correction algorithm. any error detected in the
incoming cell is treated as an uncorrectable error, and the cell is dropped.
Controls the dropping of cells when an incorrectable HEC error is
detected. When disabled, cells with uncorrectable errors are dropped.
However, when set to a logic one, cells are passed to the TM layer
regardless of the errors detected. The HEC verification state machine is
always in the correction mode. cells are always dropped when the cell
delineation state machine is in the hunt or presync states.
Controls the addition of the coset polynomial. When a logic one, the coset
polynomial is added to the header prior to comparison.
Controls the descrambling of the cell payload. When asserted high,
payload scrambling is disabled.
Reset rx FIFO. Used to reset the four cell receive FIFO when asserted to
a logic one.The FIFO ignores all writes until this bit is cleared.
Bit 6
R/W
parity
Bit 5
R/W
pass
Bit 4
R/W
corDis
Bit 3
R/W
HECdis
Bit 2
R/W
csetAdd
Bit 1
R/W
scrDis
Bit 0
R/W
rxFIFOrst
RECEIVE CELL INTERRUPTS & INTERRUPT ENABLE REGISTER
ADDRESS 0X51
DEFAULT = 8’B000XXXX0
Bit
Bit 7
Type
R/W
Symbol
OCDIEn
Function
Out of cell delineation interrupt enable. If set to logic one, an interrupt is
generated if an OCD change is detected
Correctable or incorrectable HEC error interrupt enable. If set to logic one,
an interrupt is generated if a correctable or uncorrectable error is detected
FIFO overflow interrupt enable. If set to logic one, an interrupt is
generated if a FIFO overrun is detected
Out of cell delineation interrupt. Set when the OCD signal changes
value. This bit is cleared following a read to this register.
Correctable HEC error interrupt is asserted when a correctable HEC error is
detected. This bit is cleared following a read to this register.
Uncorrectable HEC error interrupt is asserted when an uncorrectable HEC error
is detected. This bit is cleared following a read to this register.
FIFO overflow interrupt is asserted when a receive FIFO overflow occurs. This
bit is cleared following a read to this register.
Reserved
Bit 6
R/W
HECIEn
Bit 5
R/W
ovfIEn
Bit 4
R
OCDInt
Bit 3
R
corInt
Bit 2
R
uncorInt
Bit 1
R
ovfInt
Bit 0
—
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