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參數(shù)資料
| 型號： | IDT77155L155PX |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | PHY (TC-PMD) USER NETWORK INTERFACE FOR 155 MBPS ATM NETWORK APPLICATIONS |
| 中文描述： | ATM NETWORK INTERFACE, PQFP128 |
| 封裝： | 20 X 14 MM, PLASTIC, QFP-128 |
| 文件頁數(shù)： | 4/50頁 |
| 文件大?。?/td> | 307K |
| 代理商： | IDT77155L155PX |
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8.03
4
IDT77155
155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE
ADVANCED INFORMATION
Commercial Temperature Range
Symbol
A0-A7
Name
I/O
Description
Address
I
Address bus to select specific registers in the register set. The address pin A7 has an
integral pull-down resistor.
Pin #: A0/119, A1/120, A2/121, A3/122, A4/123, A5/124, A6/125, A7/126
These pins should be physically isolated from the other ground pins.
Pin #: 5, 7, 11, 29, 31, 35, 37
Latches the address bus when low, and is transparent when high. It allows interfacing to a
multiplexed address/data bus. ALE has an integral pull-up resistor.
Pin #: 127
Differential inputs indicate a loss of receive signal power. When ALOS+/- is asserted, data
on the RXD+/- inputs is squelched and the receive data/clock recovery PLL switches
to the reference clock. ALOS+/- has an effect only when RBYP is disabled. These inputs
must be dc-coupled.
Pin #: ALOS+ 28, ALOS- 27
Test pin for the transmit clock synthesis logic. When asserted, the TNB output of the clock
synthesis block is reflected on the LFO pin. ATP1 has an integral pull-down resistor.
Pin #: 40
Test pin for the receive clock/data recovery logic. When asserted, the CNB output of the clock
recovery block is reflected on the LF-pin. ATP2 has an integral pull-down resistor.
Pin #: 3
These power pins should be physically isolated from the other power pins and connected to a
well coupled 5v dc source.
Pin #: 4, 6, 8, 24, 30, 32, 36
Active low chip select to access registers.
Pin #: 100
Bidirectional data bus for register access during register reads and writes.
Pin #: D0/109, D1/110, D2/111, D3/112, D4/115, D5/116, D6/117, D7/118
Core, Ring and Thermal Grounds.
Pin #: 1, 19, 21, 38, 39, 56, 62, 64, 65, 72, 80, 102, 103, 106, 113, 128
Open drain interrupt signal which goes low when an interrupt source is active and unmasked
open from within the chip. This signal is cleared by appropriate reads to the interrupt
registers. INT is an open-drain output.
Pin #: 108
Special pin to output CAP voltage of the receive data/clock recovery logic when ATP2 is
enabled. Reference clock signal of the receive data/clock recovery logic.
Pin #: LF+/42, LF-/43
Special pin to output CAP voltage of the transmit clock synthesis logic when ATP1 is enabled.
Pin #: 44
When asserted, the multiphy enable signal converts the UTOPIA interface to be fully
compliant with the UTOPIA level-2 specification. In this mode, the TXADDR[1:0] and
RXADDR[1:0] bits determine the address of the device to be addressed. The default
operation of the chip is in single-phy UTOPIA level-1 mode. MPHYEN pin has an integral pull-
down resistor.
Pin #: 49
Output is asserted if line alarm indication signal (LAIS), path alarm indication signal (PAIS),
loss of signal (LOS), loss of frame (LOF), or loss of cell delineation (LOC) is detected in the
receive logic. RALM is updated on the rising edge of RCLK.
Pin #: 63
RATE inputs select the frame format and line rates for both the transmit and receive functions
RATE(1:0)
11
155.52 Mb/s, STS-3c / STM-1
10
51.84 Mb/s, STS-1
0X
Reserved
The RATE inputs have integral pull-up resistors, so the default is STS-3c
Pin #: RATE0/98, RATE1/97
AGND
Analog Ground
G
ALE
Address Latch
Enable
I
ALOS+
ALOS-
Analog Loss of
Signal
I
ATP1
Test pin
I
ATP2
Test pin
I
AVcc
Analog Power
P
CS
Chip Select
I
D1-D7
Data
I/O
GND
Ground
G
INT
Interrupt
O
LF+
Loop Filter
O
LF-
LFO
Special
O
MPHYEN
Multi-phy Enable
I
RALM
Receive Alarm
O
RATE0
RATE1
Line Rate
I
PIN DESCRIPTIONS
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| IDT77301 | UTOPIAFIFO 1 TO 4 (128 x 9 x 4) DEMULTIPLEXER-FIFO |
| IDT77301L12PF | UTOPIAFIFO 1 TO 4 (128 x 9 x 4) DEMULTIPLEXER-FIFO |
| IDT77301L12PFI | UTOPIAFIFO 1 TO 4 (128 x 9 x 4) DEMULTIPLEXER-FIFO |
| IDT77305 | UTOPIAFIFO 4 PORT MULTIPLEXER FIFO |
| IDT77911 | Octal Transceivers And Line/MOS Drivers With 3-State Outputs 20-PDIP -40 to 85 |
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| IDT77V011L155DA8 | 功能描述:INTERFACE DPI-UTOPIA 144-TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標準包裝:3,000 系列:- 應用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應商設備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
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