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| 型號(hào)： | IDT82V2108PX8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 219/292頁(yè) |
| 文件大小： | 0K |
| 描述： | IC FRAMER T1/J1/E1 8CH 128-PQFP |
| 標(biāo)準(zhǔn)包裝： | 500 |
| 控制器類型： | T1/E1/J1 調(diào)幀器 |
| 接口： | 并聯(lián) |
| 電源電壓： | 2.97 V ~ 3.63 V |
| 電流 - 電源： | 160mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 128-PQFP（14x20） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 82V2108PX8 |
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IDT82V2108
T1 / E1 / J1 OCTAL FRAMER
Functional Description
22
March 5, 2009
3.5
HDLC RECEIVER (RHDLC)
The HDLC extraction is performed in this block. The HDLC
Receiver #1, #2 and #3 in E1 mode or the HDLC Receiver #1 and #2 in
T1/J1 ESF mode of each framer operate independently.
3.5.1
E1 MODE
Three HDLC Receiver blocks (#1, #2 and #3) are employed for
each framer to extract the HDLC link from the received data stream.
Before the HDLC link is selected, the TXCISEL (b3, E1-00AH) should be
set to ‘0’. Thus, the configuration of the Link Control and Bits Select reg-
isters (addressed from 028H to 02DH) is for RHDLC. Next, select one of
the three HDLC Receiver blocks by setting the appropriate bits in the
RHDLCSEL[1:0] (b7~6, E1-00AH). The #2 and #3 blocks can also be
disabled by setting the V52DIS (b3, E1-007H). Then the position of the
HDLC link is defined as follows:
1. Set the DL_EVEN (b7, E1-028H or b7, E1-02AH or b7, E1-
02CH) and/or the DL_ODD (b6, E1-028H or b6, E1-02AH or b6, E1-
02CH) to choose the even and/or odd frames (the even frames are FAS
frames while the odd frames are NFAS frames);
2. Set the DL_TS[4:0] (b4~0, E1-028H or b4~0, E1-02AH or b4~0,
E1-02CH) to define the time slot of the assigned frame (or to set the
TS16_EN (b5, E1-028H) to choose the TS16 of the assigned frame);
3. Set the DL_BIT[7:0] (b7~0, E1-029H or b7~0, E1-02BH or b7~0,
E1-02DH) to select the bits of the assigned time slot.
Three HDLC standards for E1 are defined and one is selected as
follows:
1. Common Channel Signaling (CCS) data link (extract the bits in
the TS16);
2. V5.1 / V5.2 D-channel and C-channels (extract the bits in any
time slot except TS16);
3. Sa-bit data link.
All the functions of the selected HDLC Receiver block is enabled
only if the EN (b0, E1-048H) is set to logic 1.
A normal HDLC packet consists of the following parts as shown in
Figure 5. HDLC Packet
Every HDLC packet starts with a 7E (Hex) opening flag sequence
and ends with the same flag. Before the closing flag sequence, two
bytes of CRC-CCITT frame check sequences (FCS) are provided to
check all the HDLC data. The received FCS will be compared with the
local calculated FCS.
A FIFO buffer is used to store the HDLC packet, that is, to store the
data whose stuffed zeros have been removed and the FCS. However,
when the address matching is enabled, the first and/or second byte
compares with the address setting in the PA[7:0] (b7~0, E1-04CH) and
the SA[7:0] (b7~0, E1-04DH), and only the data matching the address
mode set in the MEN (b3, E1-048H) and the MM (b2, E1-048H) is stored
into the FIFO. When address matching is disabled, all the HDLC data
are stored. The first 7E opening flag which activates the HDLC link and
the 7F (Hex) abort sequence which deactivates the HDLC link will also
be converted to dummy bytes and stored into the FIFO regardless of the
address being matched or not. These two types of flags will also assert
the COLS (b5, E1-04AH) to indicate the HDLC link status change. The
content in the FIFO is read in the RD[7:0] (b7~0, E1-04BH), and the sta-
tus of the bytes will be reflected in the PBS[2:0] (b3~1, E1-04AH). Both
of these registers (RD[7:0] (b7~0, E1-04BH) and PBS[2:0] (b3~1, E1-
04AH)) can not be accessed at a rate greater than 1/15 of the XCK rate.
The depth of the FIFO is 128 bytes. When the FIFO is empty, the
FE (b7, E1-04AH) will be set. If data is still written into the FIFO when
the FIFO is already full, the FIFO will be over-written. The over-written
condition will be indicated by the OVR (b6, E1-04AH) and forces the
FIFO to be cleared.
A logic 1 in the PKIN (b4, E1-04AH) indicates a non-abort HDLC
packet was received. The PKIN (b4, E1-04AH) is set regardless of the
status of the FCS condition or there being an integer or non-integer
number of bytes stored in the FIFO.
The HDLC packet will be forced to terminate for four reasons:
1. The 7F abort sequence is received;
2. More than 15 successive logic ones are received in the data
stream;
3. Set the TR (b1, E1-048H) to logic 1;
4. Set the EN (b0, E1-048H) from logic 1 to logic 0 and back to logic
1.
All the above methods will deactivate the HDLC link immediately
and the latter two means will also clean the FIFO and interrupts. A new
search for the 7E opening flag is also initiated.
The interrupt sources in this block are:
1. Receiving the first 7E opening flag sequence which terminates
all ones data and activates the HDLC link;
2. Receiving the 7E closing flag sequence;
3. Receiving the abort sequence;
4. Exceeding the set point of the FIFO which is defined in the
INTC[6:0] (b6~0, E1-049);
5. Over-writing the FIFO.
Any one of the interrupt sources will assert the INTR (b0, E1-04AH)
high. Then the INT pin will be low to report the interrupt if the INTE (b7,
E1-049H) is logic 1.
3.5.2
T1/J1 MODE
In the SF format, there is no HDLC link.
In the ESF format, two HDLC Receiver blocks (#1 and #2) are
employed for each framer to extract the HDLC link. Before the HDLC
link is selected, the TXCISEL (b3, T1/J1-00DH) should be set to ‘0’.
Thus, the configuration of the Link Control and Bits Select registers
(addressed from 070H to 071H) is for the RHDLC. Then, selected by the
Flag (7E)
HDLC Data
one byte
01111110
FCS
two bytes
one byte
01111110
n bytes
n
2
Flag (7E)
store in FIFO
(remove the stuffed zero)
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