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參數(shù)資料
| 型號(hào)： | IDT82V2108PX8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 285/292頁 |
| 文件大小： | 0K |
| 描述： | IC FRAMER T1/J1/E1 8CH 128-PQFP |
| 標(biāo)準(zhǔn)包裝： | 500 |
| 控制器類型： | T1/E1/J1 調(diào)幀器 |
| 接口： | 并聯(lián) |
| 電源電壓： | 2.97 V ~ 3.63 V |
| 電流 - 電源： | 160mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 128-PQFP（14x20） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 82V2108PX8 |
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IDT82V2108
T1 / E1 / J1 OCTAL FRAMER
Functional Description
82
March 5, 2009
3.16
HDLC TRANSMITTER (THDLC)
The HDLC data insertion is performed in this block. The HDLC
Transmitters #1, #2 and #3 in E1 mode or the HDLC Transmitter #1 and
#2 in T1/J1 mode ESF format of each framer operate independently.
3.16.1
E1 MODE
Three HDLC Transmitter blocks are provided for each framer to
transmit a HDLC link. Before selecting the HDLC link, the TXCISEL (b3,
E1-0AH) should be set to ‘1’. Thus, the configuration of Link Control and
Bits Select registers (addressed from 028H to 02DH) is for THDLC. The
THDLCSEL[1:0] (b5~4, E1-00AH) select one of the three HDLC control-
lers to be accessed by the microcontroller. The #2 and #3 blocks can
also be disabled by setting the V52DIS (b3, E1-007H). The functionality
of the HDLC link can be defined as the follows:
1. Set the DL_EVEN (b7, E1-028H or b7, E1-02AH or b7, E1-
02CH) and/or the DL_ODD (b6, E1-028H or b6, E1-02AH or b6, E1-
02CH) to select the even and/or odd frames (the even frames are FAS
frames while the odd frames are NFAS frames);
2. Set the DL_TS[4:0] (b4~0, E1-028H or b4~0, E1-02AH or b4~0,
E1-02CH) to select the time slot of the assigned frame or to set the
TS16_EN (b5, E1-028H) to define TS16 of the assigned frame (this
HDLC link can only be set in the #1 block and is enabled when the CCS
is selected by the SIGEN [b6, E1-040H] and the DLEN [b5, E1-040H]);
3. Set the DL_BIT[7:0] (b7~0, E1-029H or b7~0, E1-02BH or b7~0,
E1-02DH) to select the bit of the assigned time slot.
Thereafter, the HDLC packet will replace the data on the assigned
data link. All the functions of the selected HDLC Transmitter block are
realized only if the EN (b0, E1-050H) is set to logic 1; otherwise, all ones
will be transmitted on the assigned data link.
A normal HDLC packet (refer to Figure 5) is started with a 7E (Hex)
flag, then the HDLC data is transmitted. Before closing, two bytes of
CRC-CCITT frame check sequences (FCS) are added if the CRC (b1,
E1-050H) is enabled. The HDLC packet is closed with another 7E flag.
However, if the FLGSHARE (b7, E1-050H) is set, the closing flag of the
current HDLC packet and the opening flag of the next HDLC packet are
shared.
A FIFO buffer is used to store the HDLC data written to the TD[7:0]
(b7~0, E1-055H). The UTHR[6:0] (b6~0, E1-051H) set the upper thresh-
old of the FIFO. When the data exceeds the fill level, the data will be
transmitted. The opening flag will be prepended before the data auto-
matically. The transmission will not stop until the entire HDLC data is
transmitted and the data in the FIFO is below the upper threshold. The
end of the current entire HDLC frame is set by the EOM (b3, E1-050H).
When it is set, the HDLC data should be transmitted even if it does not
exceed the upper threshold of the FIFO. The FCS, if enabled, will be
added before the closing flag automatically. Zero stuffing is automatically
performed to the serial output data when there are five consecutive ones
in the HDLC data or in the FCS. A 7F (Hex) abort sequence which deac-
tivates the current HDLC packet can be inserted anytime the ABT (b2,
E1-050H) is set. When the ABT (b2, E1-050H) is set, the current byte in
the TD[7:0] (b7~0, E1-055H) is still transmitted, and then the FIFO is
cleared and the 7F abort sequence is transmitted continuously. The low
threshold of the FIFO can be set in the LINT[6:0] (b6~0, E1-052H),
which should always be less than the value of the UTHR[6:0] (b6~0, E1-
051H). The FIFO can be cleared anytime the FIFOCLR (b6, E1-050H) is
set. Flags (7E) will consecutively be transmitted when there is no HDLC
data to be transmitted if the data link is activated.
Four interrupt sources can be derived from this block.
1. When the data in the FIFO is empty or less than the setting in the
LINT[6:0] (b6~0, E1-052H), the BLFILL (b5, E1-054H) will indicate. A
transition from logic 0 to 1 on the BLFILL (b5, E1-054H) will cause a
logic 1 in the LFILLI (b0, E1-054H). The interrupt on the INT pin will
occur when the LFILLE (b0, E1-053H) is enabled;
2. When the data in the FIFO reaches its maximum capacity - 128
bytes, the FULL (b6, E1-054H) will be set for indication. A transition from
logic 0 to 1 on the FULL (b6, E1-054H) will cause a logic 1 in the FULLI
(b3, E1-054H). The interrupt on the INT pin will occur when the FULLE
(b3, E1-053H) is enabled;
3. When the FIFO has already been filled with 128 bytes and new
data is still written to it, the FIFO will overflow and the OVRI (b2, E1-
054H) will be set for indication. The interrupt on the INT pin will occur
when the OVRE (b2, E1-053H) is enabled.
4. When the transmission is in process and it is out of data to be
transmitted in the FIFO, the FIFO is underrun and the UDRI (b1, E1-
054H) will be set for indication. The interrupt on the INT pin will occur
when the UDRE (b1, E1-053H) is enabled.
3.16.2
T1/J1 MODE
In the SF format, there is no HDLC link.
In the ESF format, two HDLC Transmitter blocks (#1 and #2) are
employed for each framer to transmit the HDLC link. Before selecting
the HDLC link, the TXCISEL (b3, T1/J1-00DH) should be set to ‘1’.
Thus, the configuration of the Link Control and Bits Select registers
(addressed from 070H to 071H) is for THDLC. Selected by the
THDLCSEL[1:0] (b5~4, T1/J1-00DH), registers in one of the two HDLC
Transmitter blocks are accessible to the microprocessor. The #1 block
transmits the HDLC link in the DL of F-bit (its position is shown in the
Table 4). The #2 block transmits the HDLC link in a channel and its posi-
tion is selected as follows:
1. Set the DL2_EVEN (b7, T1/J1-070H) and/or the DL2_ODD (b6,
T1/J1-070H) to select the even and/or odd frames;
2. Set the DL2_TS[4:0] (b4~0, T1/J1-070H) to select the channel of
the assigned frame;
3. Set the DL2_BIT[7:0] (b7~0, T1/J1-071H) to select the bit of the
assigned channel.
All the functions of the selected HDLC Transmitter block are real-
ized only if the EN (b0, T1/J1-034H) is enabled; otherwise, all ones will
be transmitted on the assigned data link.
The structure of the HDLC packet (refer to Figure 5) is the same as
it is described in the E1 mode. When the FLGSHARE (b7, T1/J1-034H)
is set, the closing flag of the current HDLC and the opening flag of the
next HDLC are shared.
A FIFO buffer is used to store the HDLC data written to the TD[7:0]
(b7~0, T1/J1-039H). The UTHR[6:0] (b6~0, T1/J1-035H) limit the upper
threshold of the FIFO. When the data exceeds the fill level, the data will
be transmitted. The opening flag will be added before the data automati-
cally. The transmission will not stop until an entire HDLC frame is trans-
mitted and the data in the FIFO is below the upper threshold. The end of
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