27 FN7973.2 April 25, 2013 Figures 46 and 47 illustrate the timing relationships for 2-byte and N-byte transfers, respectively. The " />
參數(shù)資料
型號(hào)： ISLA214S50IR1Z
廠商： Intersil
文件頁數(shù)： 20/41頁
文件大?。?/td> 0K
描述： IC ADC
標(biāo)準(zhǔn)包裝： 1
系列： *
ISLA214S50
27
FN7973.2
April 25, 2013
Figures 46 and 47 illustrate the timing relationships for 2-byte
and N-byte transfers, respectively. The operation for a 3-byte
transfer can be inferred from these diagrams.
SPI Configuration
ADDRESS 0X00: CHIP_PORT_CONFIG
Bit ordering and SPI reset are controlled by this register. Bit order
can be selected as MSB to LSB (MSB first) or LSB to MSB (LSB
first) to accommodate various micro controllers.
Bit 7 SDO Active
Bit 6 LSB First
Setting this bit high configures the SPI to interpret serial data as
arriving in LSB to MSB order.
Bit 5 Soft Reset
Setting this bit high resets all SPI registers to default values.
Bit 4 Reserved
This bit should always be set high.
Bits 3:0 These bits should always mirror bits 4:7 to avoid
ambiguity in bit ordering.
ADDRESS 0X02: BURST_END
If a series of sequential registers are to be set, burst mode can
improve throughput by eliminating redundant addressing. The
burst is ended by pulling the CSB pin high. Setting the burst_end
address determines the end of the transfer. During a write
operation, the user must be cautious to transmit the correct
number of bytes based on the starting and ending addresses.
Bits 7:0 Burst End Address
This register value determines the ending address of the burst
data.
Device Information
ADDRESS 0X08: CHIP_ID
ADDRESS 0X09: CHIP_VERSION
The generic die identifier and a revision number, respectively, can
be read from these two registers.
Device Configuration/Control
A common SPI map, which can accommodate single-channel or
multi-channel devices, is used for all Intersil ADC products.
ADDRESS 0X20: OFFSET_COARSE_ADC0
ADDRESS 0X21: OFFSET_FINE_ADC0
The input offset of the ADC core can be adjusted in fine and
coarse steps. Both adjustments are made via an 8-bit word as
detailed in Table 7. The data format is twos complement.
The default value of each register will be the result of the
self-calibration after initial power-up. If a register is to be
incremented or decremented, the user should first read the
register value then write the incremented or decremented value
back to the same register.
ADDRESS 0X22: GAIN_COARSE_ADC0
ADDRESS 0X23: GAIN_MEDIUM_ADC0
ADDRESS 0X24: GAIN_FINE_ADC0
Gain of the ADC core can be adjusted in coarse, medium and fine
steps. Coarse gain is a 4-bit adjustment while medium and fine
are 8-bit. Multiple Coarse Gain Bits can be set for a total
adjustment range of ±4.2%. (‘0011’
-4.2% and ‘1100’ +4.2%)
It is recommended to use one of the coarse gain settings (-4.2%,
-2.8%, -1.4%, 0, 1.4%, 2.8%, 4.2%) and fine-tune the gain using the
registers at 0x0023 and 0x24.
The default value of each register will be the result of the
self-calibration after initial power-up. If a register is to be
incremented or decremented, the user should first read the
register value then write the incremented or decremented value
back to the same register.
TABLE 6. BYTE TRANSFER SELECTION
[W1:W0]
BYTES TRANSFERRED
00
1
01
2
10
3
11
4 or more
TABLE 7. OFFSET ADJUSTMENTS
PARAMETER
0x20[7:0]
COARSE OFFSET
0x21[7:0]
FINE OFFSET
Steps
255
–Full Scale (0x00)
-133LSB (-47mV)
-5LSB (-1.75mV)
Mid–Scale (0x80)
0.0LSB (0.0mV)
0.0LSB
+Full Scale (0xFF)
+133LSB (+47mV)
+5LSB (+1.75mV)
Nominal Step Size
1.04LSB (0.37mV)
0.04LSB (0.014mV)
TABLE 8. COARSE GAIN ADJUSTMENT
0x22[3:0] core 0
0x26[3:0] core 1
NOMINAL COARSE GAIN ADJUST
(%)
Bit3
+2.8
Bit2
+1.4
Bit1
-2.8
Bit0
-1.4
TABLE 9. MEDIUM AND FINE GAIN ADJUSTMENTS
PARAMETER
0x23[7:0]
MEDIUM GAIN
0x24[7:0]
FINE GAIN
Steps
256
–Full Scale (0x00)
-2%
-0.20%
Mid–Scale (0x80)
0.00%
+Full Scale (0xFF)
+2%
+0.2%
Nominal Step Size
0.016%
0.0016%
相關(guān)PDF資料
PDF描述
ISLA222P13IRZ IC ADC 12BIT SRL/SPI 72QFN
ISLA224S25IR1Z IC ADC
KAD2708C-27Q68 IC ADC 8BIT 275MSPS PAR 68-QFN
KAD2708L-27Q68 IC ADC 8BIT 275MSPS PAR 68-QFN
KAD2710C-27Q68 IC ADC 10BIT 275MSPS PAR 68-QFN
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISLA214S50IR48EV1Z 制造商:Intersil Corporation 功能描述:ISLA214S50IRZ EVALUATION BOARD 1 48LD QFN ROHS COMPLIANT - Bulk 制造商:Intersil Corporation 功能描述:ISLA214S50IRZ EVALUATION BOARD 1 48LD QFN ROHS COMPLIANT
ISLA216IR72EV1Z 制造商:Intersil Corporation 功能描述:ISLA216IR72 EVAL BOARD - 72 LD QFN - SINGLE 16-BIT 250MSPS U - Bulk 制造商:Intersil Corporation 功能描述:EVAL BOARD FOR ISLA216IR72 制造商:Intersil Corporation 功能描述:EVAL BOARD ADC ISLA216P 制造商:Intersil Corporation 功能描述:EVAL BOARD, ADC, ISLA216P 制造商:Intersil 功能描述:ISLA216IR72 EVALRD 72LD SNGL 16-BIT 制造商:Intersil Corporation 功能描述:EVAL BOARD, ADC, ISLA216P; Silicon Manufacturer:Intersil; Silicon Core Number:ISLA216P; Kit Application Type:Data Converter; Application Sub Type:ADC; Kit Contents:Evaluation Board for ISLA216P ADC
ISLA216P 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:16-Bit, 250MSPS/200MSPS/130MSPS ADC
ISLA216P_1104 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:16-Bit, 250MSPS/200MSPS/130MSPS ADC
ISLA216P13 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:12-Bit, 500MSPS ADC Programmable Built-in Test Patterns
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*