5 FN7973.2 April 25, 2013 Absolute Maximum Ratings Thermal Information AVDD to AVSS . . . . . . . . . . . . . . . . . . . . . . . . " />
參數(shù)資料
型號： ISLA214S50IR1Z
廠商： Intersil
文件頁數(shù)： 37/41頁
文件大?。?/td> 0K
描述： IC ADC
標準包裝： 1
系列： *
ISLA214S50
5
FN7973.2
April 25, 2013
Absolute Maximum Ratings
Thermal Information
AVDD to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.4V to 2.1V
OVDD to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.4V to 2.1V
AVSS to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V
Analog Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V
Clock Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V
Logic Input to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V
Logic Inputs to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V
Latchup (Tested per JESD-78C;Class 2,Level A . . . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
48 Ld QFN (Notes 3, 4, 5) . . . . . . . . . . . . . .
23
0.75
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
3.
θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
4. For
θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
5. For solder stencil layout and reflow guidelines, please see Tech Brief TB389.
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
TA = -40°C to +85°C (typical specifications at +25°C), AIN = -2dBFS, fSAMPLE = Maximum Conversion Rate (per speed grade). Boldface limits apply
over the operating temperature range, -40°C to +85°C.
PARAMETER
SYMBOL
CONDITIONS
ISLA214S50
ISLA214S35
UNITS
MIN
(Note 6)
TYP
MAX
(Note 6)
MIN
(Note 6)
TYP
MAX
(Note 6)
DC SPECIFICATIONS
Analog Input
Full-Scale Analog Input
Range
VFS
Differential
1.95
2.00
2.15
1.95
2.00
2.15
VP-P
Input Resistance
RIN
Differential
600
Ω
Input Capacitance
CIN
Differential
13.3
pF
Full Scale Range Temp. Drift
AVTC
Full Temp
100
ppm/°C
Input Offset Voltage
VOS
-5.0
±1
5.0
-5.0
±1
5.0
mV
Gain Error
EG
-2.6
%
Common-Mode Output
Voltage
VCM
0.94
V
Common Mode Input Current
(per pin)
ICM
6.0
A/MSPS
Clock Inputs
Inputs Common Mode
Voltage
0.9
V
CLKP, CLKN Swing
1.8
V
Power Requirements
1.8V Analog Supply Voltage
AVDD
1.7
1.8
1.9
1.7
1.8
1.9
V
1.8V Digital Supply Voltage
OVDD
1.7
1.8
1.9
1.7
1.8
1.9
V
1.8V Analog Supply Current
IAVDD
359
385
313
mA
1.8V Digital Supply Current
IOVDD
I2E on, Fs/4 filter on,
Minimum number of lanes
active
222
248
159
mA
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