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參數(shù)資料
| 型號： | ISLA214S50IR1Z |
| 廠商： | Intersil |
| 文件頁數(shù)： | 24/41頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC |
| 標準包裝： | 1 |
| 系列： | * |
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ISLA214S50
30
FN7973.2
April 25, 2013
ADDRESS 0X71: PHASE_SLIP
When using the clock_divide feature, the sample clock edge that the
ADC uses to sample the analog input signal can be one of several
different edges on the incoming higher frequency sample clock. For
example, in clock_divide = 2 mode, every other incoming sample clock
edge gets used by the ADC to sample the analog input. The phase_slip
feature allows the system to control which edge of the incoming sample
clock signals gets used to cause the sampling event, by “slipping” the
sampling event by one input clock period each time phase_slip is
asserted.
The clkdivrst feature can work in conjunction with phase_slip.
After well-timed assertion of the clkdivrst signal (via overloading
on the SYNC inputs), the sampling edge position with respect to
the incoming clock rate will have been reset, allowing the system
to “slip” whatever desired number of incoming clock periods
from a known state.
ADDRESS 0X72: CLOCK_DIVIDE
The ADC has a selectable clock divider that can be set to divide
by two or one (no division). By default, the tri-level CLKDIV pin
selects the divisor This functionality can be overridden and
controlled through the SPI, as shown in Table 12. This register is
not changed by a Soft Reset.
ADDRESS 0X73: OUTPUT_MODE_A
The output_mode_A register controls the logical coding of the
sample data. Data can be coded in three possible formats: two’s
complement(default), Gray code or offset binary. See Table 13.
This register is not changed by a Soft Reset.
ADDRESS 0X74: OUTPUT_MODE_B
Bit 6 DLL Range
This bit sets the DLL operating range to fast (default) or slow.
Internal clock signals are generated by a delay-locked loop (DLL),
which has a finite operating range. Table 14 shows the allowable
sample rate ranges for the slow and fast settings.
ADDRESS 0X77: SYNC_FUNCTION
Bit 0 Clkdivrst
This bit controls the functionality of the SYNCP, SYNCN pins on
this device. By default this bit equals ‘0’, which means that the
functionality of the SYNCP, SYNCN pins is the JESD204 SYNC.
Setting this bit equal to ‘1’ modifies the functionality of the
SYNCP, SYNCN pins to be clkdivrst, which is a synchronous
divider reset on all internal dividers in the device. Usage of this
clkdivrst functionality is required to support multi-chip time
alignment and deterministic latency for devices that use
interleaved product configurations (ISLA214S50 and
ISLA214S35), and for any other product configuration that uses
clkdiv > 1. In both states, the setup and hold times with respect
to the sample clock remain the same. Contact the factory for
more details.
ADDRESS 0XB6: CALIBRATION STATUS
The LSB at address 0xB6 can be read to determine calibration
status. The bit is ‘0’ during calibration and goes to a logic ‘1’
when calibration is complete.This register is unique in that it can
be read after POR at calibration, unlike the other registers on
chip, which can’t be read until calibration is complete.
DEVICE TEST
The device can produce preset or user defined patterns on the
digital outputs to facilitate in-situ testing. A user can pick from
preset built-in patterns by writing to the output test mode field
[7:4] at 0xC0 or user defined patterns by writing to the user test
mode field [2:0] at 0xC0. The user defined patterns should be
loaded at address space 0xC1 through 0xD0, see the “SPI
Memory Map” on page 33 for more detail. The test mode is
enabled asynchronously to the sample clock, therefore several
sample clock cycles may elapse before the data is present on the
output bus.
ADDRESS 0XC0: TEST_IO
Bits 7:4 Output Test Mode
These bits set the test mode according to the description in
Bits 2:0 User Test Mode
The three LSBs in this register determine the test pattern in
combination with registers 0xC1 through 0xD0. Refer to the
TABLE 11. DIFFERENTIAL SKEW ADJUSTMENT
PARAMETER
0x70[7:0]
DIFFERENTIAL SKEW
Steps
256
–Full Scale (0x00)
-6.5ps
Mid–Scale (0x80)
0.0ps
+Full Scale (0xFF)
+6.5ps
Nominal Step Size
51fs
TABLE 12. CLOCK DIVIDER SELECTION
VALUE
0x72[2:0]
CLOCK DIVIDER
000
Pin Control
001
Divide by 1
010
Divide by 2
other
Not Allowed
TABLE 13. OUTPUT FORMAT CONTROL
VALUE
0x73[2:0]
OUTPUT FORMAT
000
Two’s Complement (Default)
010
Gray Code
100
Offset Binary
TABLE 14. DLL RANGES
DLL RANGE
MIN
MAX
UNIT
Slow
80
200
MSPS
Fast
160
500
MSPS
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