9 FN7973.2 April 25, 2013 Switching Specifications Boldface limits apply over the operating " />
參數(shù)資料
型號(hào)： ISLA214S50IR1Z
廠商： Intersil
文件頁(yè)數(shù)： 41/41頁(yè)
文件大小： 0K
描述： IC ADC
標(biāo)準(zhǔn)包裝： 1
系列： *
ISLA214S50
9
FN7973.2
April 25, 2013
Switching Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C.
PARAMETER
SYMBOL
CONDITION
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
ADC OUTPUT
Aperture Delay
tA
240
ps
RMS Aperture Jitter
jA
90
fs
Synchronous Clock Divider Reset Recovery Time (Note 12)
tRSTRT
DLL recovery
time after
Synchronous
Reset
250
s
Latency (ADC Pipeline Delay)
L
20
cycles
Overvoltage Recovery
tOVR
2cycles
SERDES
PLL Lock Time
250
s
PLL Bandwidth
2.2
MHz
Added Random Jitter
5ps
RMS
Added Deterministic Jitter
7ps P-P
Maximum Input Sample Clock Total Jitter to Maintain SERDES
BER <1E-12
Integrated from
1kHz to 10MHz
offset from
carrier
5ps rms
LVDS Inputs
SYNCP, SYNCN Setup Time (with Respect to the Positive Edge of
CLKP)
tRSTS
AVDD,
OVDD = 1.7V to
1.9V, TA = -40°C
to +85°C
400
75
ps
SYNCP, SYNCN Hold Time (with Respect to the Positive Edge of
CLKP)
tRSTH
AVDD,
OVDD = 1.7V to
1.9V, TA = -40°C
to +85°C
150
350
ps
CML Outputs
Output Rise Time
tR
165
ps
Output Fall Time
tF
145
ps
Data Output Duty Cycle
50
%
Differential Output Resistance
100
Differential Output Voltage (Note 13)
760
mVP-P
SPI INTERFACE (Notes 14, 15)
SCLK Period
t
CLK
Write Operation
14
cycles
tCLK
Read Operation
32
cycles
CSB
↓ to SCLK↑ Setup Time
tS
Read or Write
4
cycles
CSB
↑ after SCLK↑ Hold Time
tH
Read or Write
10
cycles
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