- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄2002 > ISLA214S50IR1Z (Intersil)IC ADC PDF資料下載
參數(shù)資料
| 型號(hào)： | ISLA214S50IR1Z |
| 廠商： | Intersil |
| 文件頁(yè)數(shù)： | 27/41頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)當(dāng)前第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)
ISLA214S50
33
FN7973.2
April 25, 2013
ADDRESS 0XF3: JESD204_CML_POLARITY
0xF3 Bit[2:0]: “TX polarity flip lane x” This register allows the
system designer to invert the sense of the SERDES pins on a per
lane basis. For example, writing a ‘1’ to Bit[0] causes LANE0N to
functionally become LANE0P and LANE0P to become LANE0N.
This feature allows the system designer to avoid having to
crossover P and N sides of the CML pair on the board to match
pin out and layout of the transmitter and receiver. Typically, a
trace crossover would require vias, which can degrade the signal
integrity of the high-speed SERDES lanes.
SPI Memory Map
ADDR.
(Hex)
PARAMETER NAME
BIT 7
(MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
(LSB)
DEF. VALUE
(HEX)
SP
ICo
nf
ig
/C
on
tr
ol
00
port_config
SDO Active LSB First
Soft Reset
Mirror (bit5) Mirror (bit6) Mirror (bit7)
00h
01
Reserved
02
burst_end
Burst end address [7:0]
00h
03-07
Reserved
DU
TIn
fo
08
chip_id
Chip ID #
Read only
09
chip_version
Chip Version #
Read only
0A-0F
Reserved
D
evice
Co
nfig
/C
on
tr
ol 10-1F
Reserved
20
offset_coarse_adc0
Coarse Offset
cal. value
21
offset_fine_adc0
Fine Offset
cal. value
22
gain_coarse_adc0
Reserved
Coarse Gain
cal. value
23
gain_medium_adc0
Medium Gain
cal. value
24
gain_fine_adc0
Fine Gain
cal. value
25
modes_adc0
Reserved
Power Down Mode ADC0 [2:0]
000 = Pin Control
001 = Normal Operation
010 = Nap
100 = Sleep
Other codes = Reserved
00h
NOT reset by
Soft Reset
26
offset_coarse_adc1
Coarse Offset
cal. value
27
offset_fine_adc1
Fine Offset
cal. value
28
gain_coarse_adc1
Reserved
Coarse Gain
cal. value
29
gain_medium_adc1
Medium Gain
cal. value
2A
gain_fine_adc1
Fine Gain
cal. value
2B
modes_adc1
Reserved
Power Down Mode ADC1 [2:0]
000 = Pin Control
001 = Normal Operation
010 = Nap
100 = Sleep
Other codes = Reserved
00h
NOT reset by
Soft Reset
2C-2F
Reserved
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISLA222P13IRZ | IC ADC 12BIT SRL/SPI 72QFN |
| ISLA224S25IR1Z | IC ADC |
| KAD2708C-27Q68 | IC ADC 8BIT 275MSPS PAR 68-QFN |
| KAD2708L-27Q68 | IC ADC 8BIT 275MSPS PAR 68-QFN |
| KAD2710C-27Q68 | IC ADC 10BIT 275MSPS PAR 68-QFN |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISLA214S50IR48EV1Z | 制造商:Intersil Corporation 功能描述:ISLA214S50IRZ EVALUATION BOARD 1 48LD QFN ROHS COMPLIANT - Bulk 制造商:Intersil Corporation 功能描述:ISLA214S50IRZ EVALUATION BOARD 1 48LD QFN ROHS COMPLIANT |
| ISLA216IR72EV1Z | 制造商:Intersil Corporation 功能描述:ISLA216IR72 EVAL BOARD - 72 LD QFN - SINGLE 16-BIT 250MSPS U - Bulk 制造商:Intersil Corporation 功能描述:EVAL BOARD FOR ISLA216IR72 制造商:Intersil Corporation 功能描述:EVAL BOARD ADC ISLA216P 制造商:Intersil Corporation 功能描述:EVAL BOARD, ADC, ISLA216P 制造商:Intersil 功能描述:ISLA216IR72 EVALRD 72LD SNGL 16-BIT 制造商:Intersil Corporation 功能描述:EVAL BOARD, ADC, ISLA216P; Silicon Manufacturer:Intersil; Silicon Core Number:ISLA216P; Kit Application Type:Data Converter; Application Sub Type:ADC; Kit Contents:Evaluation Board for ISLA216P ADC |
| ISLA216P | 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:16-Bit, 250MSPS/200MSPS/130MSPS ADC |
| ISLA216P_1104 | 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:16-Bit, 250MSPS/200MSPS/130MSPS ADC |
| ISLA216P13 | 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:12-Bit, 500MSPS ADC Programmable Built-in Test Patterns |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。