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參數(shù)資料
| 型號： | ISLA214S50IR1Z |
| 廠商： | Intersil |
| 文件頁數(shù)： | 21/41頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
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ISLA214S50
28
FN7973.2
April 25, 2013
ADDRESS 0X25: MODES
Two distinct reduced power modes can be selected. By default,
the tri-level NAPSLP pin can select normal operation, nap or
sleep modes (refer to “Nap/Sleep” on page 19). This functionality
can be overridden and controlled through the SPI. However, if the
ADC is powered-on with the NAPSLP pin in either Nap or Sleep
modes, the pin must first be set to Normal before the SPI port
will be enabled. Therefore, before the SPI port can be used to
override the NAPSLP pin setting, the ADC must have been put
into Normal mode at least once using the NAPSLP pin. This
register is not changed by a Soft Reset.
ADDRESS 0X26: OFFSET_COARSE_ADC1
ADDRESS 0X27: OFFSET_FINE_ADC1
The input offset of ADC core#1 can be adjusted in fine and
coarse steps in the same way that offset for core#0 can be
adjusted. Both adjustments are made via an 8-bit word as
detailed in Table 7. The data format is two’s complement.
The default value of each register will be the result of the
self-calibration after initial power-up. If a register is to be
incremented or decremented, the user should first read the
register value then write the incremented or decremented value
back to the same register.
ADDRESS 0X28: GAIN_COARSE_ADC1
ADDRESS 0X29: GAIN_MEDIUM_ADC1
ADDRESS 0X2A: GAIN_FINE_ADC1
Gain of ADC core #1 can be adjusted in coarse, medium and fine
steps in the same way that core #0 can be adjusted. Coarse gain is
a 4-bit adjustment while medium and fine are 8-bit. Multiple
Coarse Gain Bits can be set for a total adjustment range of ±4.2.
ADDRESS 0X30: I2E STATUS
The I2E general status register.
Bits 0 and 1 indicate if the I2E circuitry is in Active Run or Hold state.
The state of the I2E circuitry is dependent on the analog input signal
itself. If the input signal obscures the interleave mismatched
artifacts such that I2E cannot estimate the mismatch, the algorithm
will dynamically enter the Hold state. For example, a DC mid-scale
input to the A/D does not contain sufficient information to estimate
the gain and sample time skew mismatches, and thus the I2E
algorithm will enter the Hold state. In the Hold state, the analog
adjustments for interleave correction will be frozen and mismatch
estimate calculations will cease until such time as the analog input
achieves sufficient quality to allow the I2E algorithm to make
mismatch estimates again.
Bit 0: 0 = I2E has not detected a low power condition. 1 = I2E has
detected a low power condition, and the analog adjustments for
interleave correction are frozen.
Bit 1: 0 = I2E has not detected a low AC power condition. 1 = I2E has
detected a low AC power condition, and I2E will continue to correct
with best known information but will not update its interleave
correction adjustments until the input signal achieves sufficient AC
RMS power.
Bit 2: When first started, the I2E algorithm can take a significant
amount of time to settle (~1s), dependent on the characteristics of
the analog input signal. 0 = I2E is still settling, 1 = I2E has
completed settling.
ADDRESS 0X31: I2E CONTROL
The I2E general control register. This register can be written while
I2E is running to control various parameters.
Bit 0: 0 = turn I2E off, 1= turn I2E on
Bit 1: 0 = no action, 1 = freeze I2E, leaving all settings in the current
state. Subsequently writing a 0 to this bit will allow I2E to continue
from the state it was left in.
Bit 2-4: Disable any of the interleave adjustments of offset, gain, or
sample time skew
Bit 5: 0 = bypass notch filter, 1 = use notch filter on incoming data
before estimating interleave mismatch terms
ADDRESS 0X32: I2E STATIC CONTROL
The I2E general static control register. This register must be written
prior to turning I2E on for the settings to take effect.
Bit 1-4: Reserved, always set to 0
Bit 5: 0 = normal operation, 1 = skip coarse adjustment of the
offset, gain, and sample time skew analog controls when I2E is first
turned on. This bit would typically be used if optimal analog
adjustment values for offset, gain, and sample time skew have been
preloaded in order to have the I2E algorithm converge more quickly.
The system gain of the pair of interleaved core A/Ds can be set by
programming the medium and fine gain of the reference A/D before
turning I2E on. In this case, I2E will adjust the non-reference A/D’s
gain to match the reference A/D’s gain.
Bit 7: Reserved, always set to 0
ADDRESS 0X4A: I2E POWER DOWN
This register provides the capability to completely power down the
I2E algorithm and the Notch filter. This would typically be done to
conserve power.
BIT 0: Power down the I2E Algorithm
BIT 1: Power down the Notch Filter
ADDRESS 0X50-0X55: I2E FREEZE THRESHOLDS
This group of registers provides programming access to configure
I2E’s dynamic freeze control. As with any interleave mismatch
correction algorithm making estimates of the interleave mismatch
errors using the digitized application input signal, there are certain
characteristics of the input signal that can obscure the mismatch
estimates. For example, a DC input to the A/D contains no
TABLE 10. POWER-DOWN CONTROL
VALUE
0x25[2:0]
POWER DOWN MODE
000
Pin Control
001
Normal Operation
010
Nap Mode
100
Sleep Mode
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