- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄2002 > ISLA214S50IR1Z (Intersil)IC ADC PDF資料下載
參數(shù)資料
| 型號： | ISLA214S50IR1Z |
| 廠商： | Intersil |
| 文件頁數(shù)： | 22/41頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC |
| 標準包裝： | 1 |
| 系列： | * |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁當前第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁
ISLA214S50
29
FN7973.2
April 25, 2013
information about the sample time skew mismatch between the
core A/Ds, and thus should not be used by the I2E algorithm to
update its sample time skew estimate. Under such circumstances,
I2E enters Hold state. In the Hold state, the analog adjustments will
be frozen and mismatch estimate calculations will cease until such
time as the analog input achieves sufficient quality to allow the I2E
algorithm to make mismatch estimates again.
These registers allow the programming of the thresholds of the
meters used to determine the quality of the input signal. This can be
used by the application to optimize I2E’s behavior based on
knowledge of the input signal. For example, if a specific application
had an input signal that was typically 30dB down from full scale,
and was primarily concerned about analog performance of the A/D
at this input power, lowering the RMS power threshold would allow
I2E to continue tracking with this input power level, thus allowing it
to track over voltage and temperature changes.
0x50 (LSBs), 0x51 (MSBs) RMS Power Threshold
This 16-bit quantity is the RMS power threshold at which I2E will
enter Hold state. The RMS power of the analog input is calculated
continuously by I2E on incoming data.
Only the upper 12 bits of the ADC sample outputs are used in the
averaging process for comparison to the power threshold registers.
A 12-bit number squared produces a 24-bit result (for A/D
resolutions under 12-bits, the A/D samples are MSB-aligned to
12-bit data). A dynamic number of these 24-bit results are averaged
to compare with this threshold approximately every 1s to decide
whether or not to freeze I2E. The 24-bit threshold is constructed with
bits 23 through 20 (MSBs) assigned to 0, bits 19 through 4 assigned
to this 16-bit quantity, and bits 3 through 0 (LSBs) assigned to 0. As
an example, if the application wanted to set this threshold to trigger
near the RMS analog input of a -20dBFS sinusoidal input, the
calculation to determine this register’s value would be as shown by
Therefore, programming 0x1488 into these two registers will cause
I2E to freeze when the signal being digitized has less RMS power
than a -20dBFS sinusoid.
The default value of this register is 0x1000, causing I2E to freeze
when the input amplitude is less than -21.2 dBFS.
The freezing of I2E by the RMS power meter threshold affects the
gain and sample time skew interleave mismatch estimates, but not
the offset mismatch estimate.
0x52 RMS Power Hysteresis
In order to prevent I2E from constantly oscillating between the
Hold and Track state, there is hysteresis in the comparison
described above. After I2E enters a frozen state, the RMS input
power must achieve threshold value + hysteresis to again enter
the Track state. The hysteresis quantity is a 24-bit value,
constructed with bits 23 through 12 (MSBs) being assigned to 0,
bits 11 through 4 assigned to this register’s value, and bits 3
through 0 (LSBs) assigned to 0.
0X53(LSBS), 0X54(MSBS) AC RMS POWER
THRESHOLD
Similar to RMS power threshold, there must be sufficient AC RMS
power (or dV/dt) of the input signal to measure sample time skew
mismatch for an arbitrary input. This is clear from observing the
effect when a high voltage (and therefore large RMS value) DC input
is applied to the A/D input. Without sufficient dV/dt in the input
signal, no information about the sample time skew between the
core A/Ds can be determined from the digitized samples. The AC
RMS Power Meter is implemented as a high-passed (via DSP) RMS
power meter.
The required algorithm is documented as follows.
1. Write the MSBs of the 16-bit quantity to SPI Address 0x54
2. Write the LSBs of the 16-bit quantity to SPI Address 0x53
Only the upper 12 bits of the ADC sample outputs are used in the
averaging process for comparison to the power threshold registers.
A 12-bit number squared produces a 24-bit result (for A/D
resolutions under 12-bits, the A/D samples are MSB-aligned to
12-bit data). A dynamic number of these 24-bit results are averaged
to compare with this threshold approximately every 1s to decide
whether or not to freeze I2E. The 24-bit threshold is constructed with
bits 23 through 20 (MSBs) assigned to 0, bits 19 through 4 assigned
to this 16-bit quantity, and bits 3 through 0 (LSBs) assigned to 0. The
calculation methodology to set this register is identical to the
description in the RMS power threshold description.
The freezing of I2E when the AC RMS power meter threshold is not
met affects the sample time skew interleave mismatch estimate,
but not the offset or gain mismatch estimates.
0x55 AC RMS Power Hysteresis
In order to prevent I2E from constantly oscillating between the
Hold and Track state, there is hysteresis in the comparison
described above. After I2E enters a frozen state, the AC RMS
input power must achieve threshold value + hysteresis to again
enter the Track state. The hysteresis quantity is a 24-bit value,
constructed with bits 23 through 12 (MSBs) being assigned to 0,
bits 11 through 4 assigned to this register’s value, and bits 3
through 0 (LSBs) assigned to 0.
Address 0x60-0x64: I2E initialization
These registers provide access to the initialization values for each of
offset, gain, and sample time skew that I2E programs into the target
core A/D before adjusting to minimize interleave mismatch. They
can be used by the system to, for example, reduce the convergence
time of the I2E algorithm by programming in the optimal values
before turning I2E on. In this case, I2E only needs to adjust for
temperature and voltage-induced changes since the optimal values
were recorded.
Global Device Configuration/Control
ADDRESS 0X70: SKEW_DIFF
The value in the skew_diff register adjusts the timing skew
between the two A/D cores. The nominal range and resolution of
this adjustment are given in Table 11. The default value of this
register after power-up is 80h.
RMS
codes
2
-------
10
20
–
20
---------
×
2
12
290
()codes
×
=
(EQ. 2)
hex
290
()
2
()
0x14884
TruncateMSBandLSBhexdigit
0
x1488
=
(EQ. 3)
相關PDF資料 |
PDF描述 |
|---|---|
| ISLA222P13IRZ | IC ADC 12BIT SRL/SPI 72QFN |
| ISLA224S25IR1Z | IC ADC |
| KAD2708C-27Q68 | IC ADC 8BIT 275MSPS PAR 68-QFN |
| KAD2708L-27Q68 | IC ADC 8BIT 275MSPS PAR 68-QFN |
| KAD2710C-27Q68 | IC ADC 10BIT 275MSPS PAR 68-QFN |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ISLA214S50IR48EV1Z | 制造商:Intersil Corporation 功能描述:ISLA214S50IRZ EVALUATION BOARD 1 48LD QFN ROHS COMPLIANT - Bulk 制造商:Intersil Corporation 功能描述:ISLA214S50IRZ EVALUATION BOARD 1 48LD QFN ROHS COMPLIANT |
| ISLA216IR72EV1Z | 制造商:Intersil Corporation 功能描述:ISLA216IR72 EVAL BOARD - 72 LD QFN - SINGLE 16-BIT 250MSPS U - Bulk 制造商:Intersil Corporation 功能描述:EVAL BOARD FOR ISLA216IR72 制造商:Intersil Corporation 功能描述:EVAL BOARD ADC ISLA216P 制造商:Intersil Corporation 功能描述:EVAL BOARD, ADC, ISLA216P 制造商:Intersil 功能描述:ISLA216IR72 EVALRD 72LD SNGL 16-BIT 制造商:Intersil Corporation 功能描述:EVAL BOARD, ADC, ISLA216P; Silicon Manufacturer:Intersil; Silicon Core Number:ISLA216P; Kit Application Type:Data Converter; Application Sub Type:ADC; Kit Contents:Evaluation Board for ISLA216P ADC |
| ISLA216P | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:16-Bit, 250MSPS/200MSPS/130MSPS ADC |
| ISLA216P_1104 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:16-Bit, 250MSPS/200MSPS/130MSPS ADC |
| ISLA216P13 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:12-Bit, 500MSPS ADC Programmable Built-in Test Patterns |
發(fā)布緊急采購，3分鐘左右您將得到回復。