3 FN7973.2 April 25, 2013 Pin Descriptions PIN NUMBER NAME FUNCTION 2, 11, 14, 15, 46 AVDD 1.8V Analog Supply 12, 20, 47, 48 DNC Do " />
參數(shù)資料
型號: ISLA214S50IR1Z
廠商: Intersil
文件頁數(shù): 23/41頁
文件大小: 0K
描述: IC ADC
標準包裝: 1
系列: *
ISLA214S50
3
FN7973.2
April 25, 2013
Pin Descriptions
PIN NUMBER
NAME
FUNCTION
2, 11, 14, 15, 46
AVDD
1.8V Analog Supply
12, 20, 47, 48
DNC
Do Not Connect
3, 4, 9, 10
AVSS
Analog Ground
7, 8
VINP
Analog Input Positive
5, 6
VINN
Analog Input Negative
1
VCM
Common Mode Output
44
CLKDIV
Clock Divider Control
16, 17
CLKP, CLKN
Clock Input True, Complement
45
NAPSLP
Power Control (Nap, Sleep modes)
13
RESETN
Power On Reset (Active Low)
26, 29, 32, 35, 37, 38
OVSS
Output Ground
25, 36, 39
OVDD
1.8V Digital Supply
22, 24
OVDD (PLL)
1.8V Analog Supply for SERDES PLL
21, 23
OVSS (PLL)
Analog Ground Supply for SERDES PLL
18, 19
SYNCP, SYNCN
JESD204 SYNC Input
27, 28
LANE0P, LANE0N
SERDES Lane 0
30, 31
LANE1P, LANE1N
SERDES Lane 1
33, 34
LANE2P, LANE2N
SERDES Lane 2
40
SDO
SPI Serial Data Output
41
CSB
SPI Chip Select (active low)
42
SCLK
SPI Clock
43
SDIO
SPI Serial Data Input/Output
PAD
AVSS
Exposed Paddle. Analog Ground (connect to AVSS)
Ordering Information
PART NUMBER
(Notes 1, 2)
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISLA214S50IR1Z
ISLA214S50 IR1Z
-40 to +85
48 Ld QFN
L48.7x7G
Coming Soon
ISLA214S35IR1Z
ISLA214S35 IR1Z
-40 to +85
48 Ld QFN
L48.7x7G
Coming Soon
ISLA214S50IR48EV1Z
Evaluation Board
NOTES:
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate-e4
termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. For Moisture Sensitivity Level (MSL), please see device information page for ISLA214S50, ISLA214S35. For more information on MSL please see
techbrief TB363.
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