參數(shù)資料
型號(hào): ISP1583ET2
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封裝: 6 X 6 MM, 0.80 MM HEIGHT, LEAD FREE, PLASTIC, MO-195, SOT543-1,TFBGA-64
文件頁(yè)數(shù): 27/100頁(yè)
文件大?。?/td> 508K
代理商: ISP1583ET2
ISP1583_7
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 22 September 2008
31 of 99
NXP Semiconductors
ISP1583
Hi-Speed USB peripheral controller
Buffer Length
Buffer Status
Control Function
Data Port
Endpoint MaxPacketSize
Endpoint Type
Remark: Write zero to all reserved bits, unless otherwise specied.
9.2 Initialization registers
9.2.1 Address register (address: 00h)
This register sets the USB assigned address and enables the USB device. Table 22
shows the Address register bit allocation.
Bits DEVADDR[6:0] will be cleared whenever a bus reset, a power-on reset or a soft reset
occurs. Bit DEVEN will be cleared whenever a power-on reset or a soft reset occurs.
In response to standard USB request SET_ADDRESS, the rmware must write the
(enabled) device address to the Address register, followed by sending an empty packet to
the host. The new device address is activated when the device receives an
acknowledgment from the host for the empty packet token.
9.2.2 Mode register (address: 0Ch)
This register consists of 2 bytes (bit allocation: see Table 24).
The Mode register controls resume, suspend and wake-up behavior, interrupt activity, soft
reset, clock signals and SoftConnect operation.
Table 22.
Address register: bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
DEVEN
DEVADDR[6:0]
Reset
00000000
Bus reset
unchanged
0000000
Access
R/W
Table 23.
Address register: bit description
Bit
Symbol
Description
7
DEVEN
Device Enable: Logic 1 enables the device. The device will not
respond to the host, unless this bit is set.
6 to 0
DEVADDR[6:0]
Device Address: This eld species the USB device address.
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