參數(shù)資料
型號(hào): ISP1583ET2
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封裝: 6 X 6 MM, 0.80 MM HEIGHT, LEAD FREE, PLASTIC, MO-195, SOT543-1,TFBGA-64
文件頁數(shù): 68/100頁
文件大?。?/td> 508K
代理商: ISP1583ET2
ISP1583_7
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 22 September 2008
6 of 99
NXP Semiconductors
ISP1583
Hi-Speed USB peripheral controller
7.2 Pin description
Fig 4.
Pin conguration ISP1583ET1 (top view)
004aaa991
ISP1583ET1
Transparent top view
ball A1
index area
18
7
6
5
4
3
2
B
C
D
E
F
G
H
A
Table 3.
Pin description
Symbol[1]
Pin
Type[2] Description
ISP1583BS ISP1583ET;
ISP1583ET2
ISP1583ET1
AGND
1
D2
-
analog ground
RPU
2
A1
A
pull-up resistor connection; this pin must be connected to
3.3 V through an external 1.5 k
resistor to pull up pin DP
DP
3
B1
A
USB D+ line connection (analog)
DM
4
C1
A
USB D
line connection (analog)
AGND
5
-
analog ground
RREF
6
D1
A
external bias resistor connection; this pin must be
connected to ground through a 12.0 k
± 1 % resistor
RESET_N
7
E2
C3
I
reset input (500
s); a LOW level produces an
asynchronous reset; connect to VCC(3V3) for power-on
reset (internal POR circuit)
When the RESET_N pin is LOW, ensure that the WAKEUP
pin does not go from LOW to HIGH; otherwise the device
will enter test mode.
TTL; 5 V tolerant
EOT
8
E1
D3
I
end-of-transfer input (programmable polarity); used in
DMA slave mode only; when not in use, connect this pin to
VCC(I/O) through a 10 k resistor
input pad; TTL; 5 V tolerant
DREQ
9
F2
E1
I/O
DMA request input or output (programmable polarity); the
signal direction depends on bit MASTER in register DMA
Hardware (see Table 59):
Input: DMA master mode if bit MASTER = 1
Output: DMA slave mode if bit MASTER = 0
When not in use, in the default setting, this pin must be
connected to ground through a 10 k
resistor.
bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant
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