參數(shù)資料
型號(hào): ISP1583ET2
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封裝: 6 X 6 MM, 0.80 MM HEIGHT, LEAD FREE, PLASTIC, MO-195, SOT543-1,TFBGA-64
文件頁(yè)數(shù): 47/100頁(yè)
文件大?。?/td> 508K
代理商: ISP1583ET2
ISP1583_7
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 22 September 2008
49 of 99
NXP Semiconductors
ISP1583
Hi-Speed USB peripheral controller
9.4.2 DMA Transfer Counter register (address: 34h)
This 4-byte register sets up the total byte count for a DMA transfer (DMACR). It indicates
the remaining number of bytes left for transfer. The bit allocation is given in Table 54.
For IN endpoint — Because there is a FIFO in the ISP1583 DMA controller, some data
may remain in the FIFO during the DMA transfer. The maximum FIFO size is 8 bytes, and
the maximum delay time for data to be shifted to endpoint buffer is 60 ns.
For OUT endpoint — Data will not be cleared from the endpoint buffer, until all the data is
read from the DMA FIFO.
11h
Reset DMA
Reset DMA: Initializes the DMA core to its power-on reset state.
Remark: When the DMA core is reset during the Reset DMA
command, the DREQ, DACK, DIOW and DIOR handshake pins
will temporarily be asserted. This can confuse the external DMA
controller. To prevent this, start the external DMA controller only
after the DMA reset.
12h
MDMA stop
MDMA stop: This command immediately stops the MDMA data
transfer. This is applicable for commands 06h and 07h only.
13h
GDMA stop
GDMA stop: This command stops the GDMA data transfer. Any
data in the OUT endpoint that is not transferred by the DMA will
remain in the buffer. The FIFO data for the IN endpoint will be
written to the endpoint buffer. An interrupt bit will be set to
indicate the completion of the DMA Stop command.
Remark: For the DMA OUT transfer, if the DMA Burst Counter
register is programmed to some value, for example 512 bytes,
and if a GDMA Stop command is issued in the middle of a
transfer, the transfer will continue until the end of the burst size
(512 bytes). Issuing a GDMA Stop command does not allow the
ISP1583 to stop in the middle of the burst. It can only be stopped
in between bursts.
14h to 20h
-
reserved
21h
Read Task File
register 1F1h
Read Task File register 1F1h: When reading is completed, an
interrupt is generated.
22h
Read Task File
register 1F2h
Read Task File register 1F2h: When reading is completed, an
interrupt is generated.
23h
Read Task File
register 1F3h
Read Task File register 1F3h: When reading is completed, an
interrupt is generated.
24h
Read Task File
register 1F4h
Read Task File register 1F4h: When reading is completed, an
interrupt is generated.
25h
Read Task File
register 1F5h
Read Task File register 1F5h: When reading is completed, an
interrupt is generated.
26h
Read Task File
register 1F6h
Read Task File register 1F6h: When reading is completed, an
interrupt is generated.
27h
Read Task File
register 3F6h
Read Task File register 3F6h: When reading is completed, an
interrupt is generated.
28h
Read Task File
register 3F7h
Read Task File register 3F7h: When reading is completed, an
interrupt is generated.
29h to FFh
-
reserved
Table 53.
DMA commands …continued
Code
Name
Description
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