參數(shù)資料
型號(hào): ISP1583ET2
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封裝: 6 X 6 MM, 0.80 MM HEIGHT, LEAD FREE, PLASTIC, MO-195, SOT543-1,TFBGA-64
文件頁(yè)數(shù): 84/100頁(yè)
文件大?。?/td> 508K
代理商: ISP1583ET2
ISP1583_7
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 22 September 2008
83 of 99
NXP Semiconductors
ISP1583
Hi-Speed USB peripheral controller
13.2.3 MDMA mode
[1]
Tcy1 is the total cycle time, consisting of command active time tw1 and command recovery (inactive) time tw2, that is, Tcy1 = tw1 + tw2.
Minimum timing requirements for Tcy1, tw1 and tw2 must all be met. As Tcy1(min) is greater than the sum of tw1(min) and tw2(min), a host
implementation must lengthen tw1 and/or tw2 to ensure that Tcy1 is equal to or greater than the value reported in the IDENTIFY DEVICE
data. A device implementation shall support any legal host implementation.
Table 110. MDMA mode timing parameters
VCC(I/O) = 1.65 V to 3.6 V; VCC(3V3) = 3.3 V; VGND = 0 V; Tamb = 40 °C to +85 °C; unless otherwise specied.
Symbol
Parameter
Conditions
Mode 0
Mode 1
Mode 2
Unit
Tcy1(min)
read/write cycle time
[1] 480
150
120
ns
tw1(min)
DIOR or DIOW pulse width
[1] 215
80
70
ns
td1(max)
data valid delay after DIOR on
150
60
50
ns
th3(min)
data hold time after DIOR off
5
ns
tsu2(min)
data set-up time before DIOR or DIOW off
100
30
20
ns
th2(min)
data hold time after DIOW off
20
15
10
ns
tsu1(min)
DACK set-up time before DIOR or DIOW on
0
ns
th1(min)
DACK hold time after DIOR or DIOW off
20
5
ns
tw2(min)
DIOR recovery time
50
25
ns
DIOW recovery time
[1] 215
50
25
ns
td2(max)
DIOR on to DREQ off delay
120
40
35
ns
DIOW on to DREQ off delay
40
35
ns
td3(max)
DACK off to data lines 3-state delay
20
25
ns
(1) Programmable polarity: shown as active LOW.
(2) Programmable polarity: shown as active HIGH.
Fig 35. MDMA master mode timing
(write) DATA[15:0]
(read) DATA[15:0]
DREQ(2)
DACK(1)
DIOR or DIOW(1)
mgt506
Tcy1
tw1
tsu1
tw2
td2
td3
th2
th1
td1
th3
tsu2
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