參數(shù)資料
型號(hào)： ISP1583ET2
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封裝： 6 X 6 MM, 0.80 MM HEIGHT, LEAD FREE, PLASTIC, MO-195, SOT543-1,TFBGA-64
文件頁(yè)數(shù)： 58/100頁(yè)
文件大?。?/td> 508K
代理商： ISP1583ET2
ISP1583_7
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 22 September 2008
59 of 99
NXP Semiconductors
ISP1583
Hi-Speed USB peripheral controller
9.4.10 DMA Burst Counter register (address: 64h)
Table 80 shows the bit allocation of the 2-byte register.
9.5 General registers
9.5.1 Interrupt register (address: 18h)
The Interrupt register consists of 4 bytes. The bit allocation is given in Table 82.
When a bit is set in the Interrupt register, it indicates that the hardware condition for an
interrupt has occurred. When the Interrupt register content is nonzero, the INT output will
be asserted corresponding to the Interrupt Enable register. On detecting the interrupt, the
external microprocessor must read the Interrupt register and mask it with the
corresponding bits in the Interrupt Enable register to determine the source of the interrupt.
Each endpoint buffer has a dedicated interrupt bit (EPnTX, EPnRX). In addition, various
bus states can generate an interrupt: resume, suspend, pseudo SOF, SOF and bus reset.
The DMA controller only has one interrupt bit: the source for a DMA interrupt is shown in
the DMA Interrupt Reason register (see Table 72 and Table 73).
Fig 17. Programmable strobe timing
x
(N + 1) cycles
004aaa125
Table 80.
DMA Burst Counter register: bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
BURSTCOUNTER[12:8]
Reset
-
00000
Bus reset
-
00000
Access
-
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
BURSTCOUNTER[7:0]
Reset
00000010
Bus reset
00000010
Access
R/W
Table 81.
DMA Burst Counter register: bit description
Bit
Symbol
Description
15 to 13
-
reserved
12 to 0
BURSTCOUNTER
[12:0]
Burst Counter: This register denes the burst length. The
counter must be programmed to be a multiple of two in 16-bit
mode. The value of the burst counter must be programmed so
that the burst counter is a factor of the buffer size.
It is used to determine the assertion and deassertion of DREQ.
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