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參數(shù)資料
| 型號： | ISP1583ET2 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PBGA64 |
| 封裝： | 6 X 6 MM, 0.80 MM HEIGHT, LEAD FREE, PLASTIC, MO-195, SOT543-1,TFBGA-64 |
| 文件頁數(shù)： | 80/100頁 |
| 文件大?。?/td> | 508K |
| 代理商： | ISP1583ET2 |
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ISP1583_7
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 22 September 2008
79 of 99
NXP Semiconductors
ISP1583
Hi-Speed USB peripheral controller
13.2 DMA timing
13.2.1 PIO mode
Remark: In the following subsections, RW_N/RD_N, DS_N/WR_N, READY/IORDY and
ALE/A0 refer to the ISP1583 pin.
[1]
Tcy1 is the total cycle time, consisting of command active time tw1 and command recovery (inactive) time tw2, that is, Tcy1 = tw1 + tw2.
Minimum timing requirements for Tcy1, tw1 and tw2 must all be met. As Tcy1(min) is greater than the sum of tw1(min) and tw2(min), a host
implementation must lengthen tw1 and/or tw2 to ensure that Tcy1 is equal to or greater than the value reported in the IDENTIFY DEVICE
data. A device implementation shall support any legal host implementation.
[2]
td2 species the time after DIOR is negated, when the data bus is no longer driven by the device (3-state).
[3]
If READY/IORDY is LOW at tsu4, the host waits until READY/IORDY is made HIGH before the PIO cycle is completed. In that case, tsu5
must be met for reading (tsu3 does not apply). When READY/IORDY is HIGH at tsu4, tsu3 must be met for reading (tsu5 does not apply).
Table 108. PIO mode timing parameters
VCC(I/O) = 1.65 V to 3.6 V; VCC(3V3) = 3.3 V; VGND = 0 V; Tamb = 40 °C to +85 °C; unless otherwise specied.
Symbol Parameter
Conditions
Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Unit
Tcy1(min) read or write cycle time
[1] 600
383
240
180
120
ns
tsu1(min)
address to DIOR or DIOW on set-up
time
70
50
30
25
ns
tw1(min)
DIOR or DIOW pulse width
[1] 165
125
100
80
70
ns
tw2(min)
DIOR/DIOW recovery time
[1] ---70
25
ns
tsu2(min)
data set-up time before DIOW off
60
45
30
20
ns
th2(min)
data hold time after DIOW off
30
20
15
10
ns
tsu3(min)
data set-up time before DIOR on
50
35
20
ns
th3(min)
data hold time after DIOR off
5
ns
td2(max)
data to 3-state delay after DIOR off
[2] 30
30
ns
th1(min)
address hold time after DIOR or DIOW
off
20
15
10
ns
tsu4(min)
READY/IORDY after DIOR or DIOW on
set-up time
[3] 35
35
ns
tsu5(min)
read data to READY/IORDY HIGH
set-up time
[3] 00000ns
tw3(max)
READY/IORDY LOW pulse width
1250
ns
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| ISP1583ET2,518 | 功能描述:外圍驅(qū)動器與原件 - PCI USB 2.0 DEVICE RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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