參數(shù)資料
型號： ISP1583ET2
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封裝： 6 X 6 MM, 0.80 MM HEIGHT, LEAD FREE, PLASTIC, MO-195, SOT543-1,TFBGA-64
文件頁數(shù)： 59/100頁
文件大?。?/td> 508K
代理商： ISP1583ET2
ISP1583_7
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 22 September 2008
60 of 99
NXP Semiconductors
ISP1583
Hi-Speed USB peripheral controller
Each interrupt bit can individually be cleared by writing logic 1. The DMA Interrupt bit can
be cleared by writing logic 1 to the related interrupt source bit in the DMA Interrupt
Reason register, followed by writing logic 1 to the DMA bit of the Interrupt register.
Table 82.
Interrupt register: bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
reserved
EP7TX
EP7RX
Reset
------
0
Bus reset
------
0
Access
------
R/W
Bit
23
22
21
20
19
18
17
16
Symbol
EP6TX
EP6RX
EP5TX
EP5RX
EP4TX
EP4RX
EP3TX
EP3RX
Reset
00000000
Bus reset
00000000
Access
R/W
Bit
15
14
13
12
11
10
9
8
Symbol
EP2TX
EP2RX
EP1TX
EP1RX
EP0TX
EP0RX
reserved
EP0SETUP
Reset
000000
-
0
Bus reset
000000
-
0
Access
R/W
-
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
VBUS
DMA
HS_STAT
RESUME
SUSP
PSOF
SOF
BRESET
Reset
00000000
Bus reset
00000001
Access
R/W
Table 83.
Interrupt register: bit description
Bit
Symbol
Description
31 to 26
-
reserved
25
EP7TX
logic 1 indicates the endpoint 7 TX buffer as interrupt source
24
EP7RX
logic 1 indicates the endpoint 7 RX buffer as interrupt source
23
EP6TX
logic 1 indicates the endpoint 6 TX buffer as interrupt source
22
EP6RX
logic 1 indicates the endpoint 6 RX buffer as interrupt source
21
EP5TX
logic 1 indicates the endpoint 5 TX buffer as interrupt source
20
EP5RX
logic 1 indicates the endpoint 5 RX buffer as interrupt source
19
EP4TX
logic 1 indicates the endpoint 4 TX buffer as interrupt source
18
EP4RX
logic 1 indicates the endpoint 4 RX buffer as interrupt source
17
EP3TX
logic 1 indicates the endpoint 3 TX buffer as interrupt source
16
EP3RX
logic 1 indicates the endpoint 3 RX buffer as interrupt source
15
EP2TX
logic 1 indicates the endpoint 2 TX buffer as interrupt source
14
EP2RX
logic 1 indicates the endpoint 2 RX buffer as interrupt source
13
EP1TX
logic 1 indicates the endpoint 1 TX buffer as interrupt source
12
EP1RX
logic 1 indicates the endpoint 1 RX buffer as interrupt source
11
EP0TX
logic 1 indicates the endpoint 0 data TX buffer as interrupt source
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