參數(shù)資料
型號(hào)： ISP1583ET2
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封裝： 6 X 6 MM, 0.80 MM HEIGHT, LEAD FREE, PLASTIC, MO-195, SOT543-1,TFBGA-64
文件頁數(shù)： 45/100頁
文件大?。?/td> 508K
代理商： ISP1583ET2
ISP1583_7
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 22 September 2008
48 of 99
NXP Semiconductors
ISP1583
Hi-Speed USB peripheral controller
Table 52.
DMA Command register: bit description
Bit
Symbol
Description
7 to 0
DMA_CMD[7:0]
DMA command code, see Table 53.
PIO read or write that started using the DMA Command register
only performs a 16-bit transfer.
Table 53.
DMA commands
Code
Name
Description
00h
GDMA Read
Generic DMA IN token transfer (slave mode only): Data is
transferred from the external DMA bus to the internal buffer.
Strobe: DIOW by the external DMA controller.
01h
GDMA Write
Generic DMA OUT token transfer (slave mode only): Data is
transferred from the internal buffer to the external DMA bus.
Strobe: DIOR by the external DMA controller.
02h to 05h
-
reserved
06h
MDMA Read
Multi-word DMA Read: Data is transferred from the external
DMA bus to the internal buffer.
07h
MDMA Write
Multi-word DMA Write: Data is transferred from the internal
buffer to the external DMA bus.
0Ah
Read 1F0
Read at address 1F0h: Initiates a PIO read cycle from Task File
1F0. Before issuing this command, the task le byte count must
be programmed at address 1F4h (LSByte) and 1F5h (MSByte).
0Bh
Poll BSY
Poll BSY status bit for ATAPI device: Starts repeated PIO read
commands to poll the BSY status bit of the ATAPI device. When
BSY = 0, polling is terminated and an interrupt is generated. The
interrupt can be masked but the interrupt bit will still be set.
Therefore, you can manually poll this interrupt bit.
0Ch
Read Task Files
Read Task Files: Reads all task les. When Task File Index is
set to logic 0, this command reads all registers, except 1F0h and
1F7h. If Task File Index is not logic 0, the Task register of the
address set in the Task File register will be read. When the
reading is completed, an interrupt is generated. The interrupt
can be masked off, however, the interrupt bit will still be set.
Therefore, you can manually poll this interrupt bit.
0Dh
-
reserved
0Eh
Validate Buffer
Validate Buffer (for debugging only): Request from the
microcontroller to validate the endpoint buffer, following an
ATA-to-USB data transfer.
0Fh
Clear Buffer
Clear Buffer: Request from the microcontroller to clear the
endpoint buffer, after a DMA-to-USB data transfer. Logic 1 clears
the TX buffer of the indexed endpoint; the RX buffer is not
affected. The TX buffer is automatically cleared once data is
sent on the USB bus. This bit is set only when it is necessary to
forcefully clear the buffer.
Remark: If using double buffer, to clear both the buffers issue
the Clear Buffer command two times, that is, set and clear this
bit two times.
10h
Restart
Restart: Request from the microcontroller to move the buffer
pointers to the beginning of the endpoint FIFO.
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ISP1583ET-T 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI HI-SPEED USB2 DEVICE RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
ISP1583ETUM 功能描述:IC USB CTRL HI-SPEED 64TFBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A
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