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參數(shù)資料
| 型號： | KSZ8851SNLI TR |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 14/80頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ETHERNET CTLR 1PORT PCI 32MLF |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 控制器類型： | 以太網(wǎng)控制器，MAC/PHY |
| 接口： | 總線 |
| 電源電壓： | 1.8V，2.5V，3.3V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，32-MLF? |
| 供應(yīng)商設(shè)備封裝： | 32-MLF?（5x5） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁面： | 1081 (CN2011-ZH PDF) |
| 其它名稱： | 576-3506-6 |
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Micrel, Inc.
KSZ8851SNL/SNLI
August 2009
21
M9999-083109-2.0
transmitter on) with zero pause time to turn off the flow control (turn on transmission to the port). A hysteresis feature is
provided to prevent the flow control mechanism from being constantly activated and deactivated.
Half-Duplex Backpressure
A half-duplex backpressure option (non-IEEE 802.3 standards) is also provided. The activation and deactivation
conditions are the same as in full-duplex mode. If backpressure is required, the KSZ8851SNL sends preambles to defer
the other stations' transmission (carrier sense deference).
To avoid jabber and excessive deference (as defined in the 802.3 standard), after a certain time, the KSZ8851SNL
discontinues the carrier sense and then raises it again quickly. This short silent time (no carrier sense) prevents other
stations from sending out packets thus keeping other stations in a carrier sense deferred state. If the port has packets to
send during a backpressure situation, the carrier sense type backpressure is interrupted and those packets are
transmitted instead. If there are no additional packets to send, carrier sense type backpressure is reactivated again until
chip resources free up. If a collision occurs, the binary exponential back-off algorithm is skipped and carrier sense is
generated immediately, thus reducing the chance of further collision and carrier sense is maintained to prevent packet
reception.
Address Filtering Function
The KSZ8851SNL supports 11 different address filtering schemes as shown in the following Table 3. The Ethernet
destination address (DA) field inside the packet is the first 6-byte field which uses to compare with either the host MAC
address registers (0x10 – 0x15) or the MAC address hash table registers (0xA0 – 0xA7) for address filtering operation.
The first bit (bit 40) of the destination address (DA) in the Ethernet packet decides whether this is a physical address if bit
40 is “0” or a multicast address if bit 40 is “1”.
Receive Control Register (0x74 – 0x75): RXCR1
Item
Address Filtering
Mode
RX All
(Bit 4)
RX Inverse
(Bit 1)
RX Physical
Address
(Bit 11)
RX Multicast
Address
(Bit 8)
Description
1
Perfect
0
1
All Rx frames are passed only if the DA exactly matches the
MAC address in MARL, MARM and MARH registers.
2
Inverse perfect
0
1
All Rx frames are passed if the DA is not matching the MAC
address in MARL, MARM and MARH registers.
3
Hash only
0
All Rx frames with either multicast or physical destination
address are filtering against the MAC address hash table.
4
Inverse hash only
0
1
0
All Rx frames with either multicast or physical destination
address are filtering not against the MAC address hash table.
All Rx frames which are filtering out at item 3 (Hash only) only
are passed in this mode.
5
Hash perfect
(Default)
0
1
0
All Rx frames are passed with Physical address (DA) matching
the MAC address and to enable receive multicast frames that
pass the hash table when Multicast address is matching the
MAC address hash table.
6
Inverse hash
perfect
0
1
0
All Rx frames which are filtering out at item 5 (Hash perfect) only
are passed in this mode.
7
Promiscuous
1
0
All Rx frames are passed without any conditions.
8
Hash only with
Multicast address
passed
1
0
All Rx frames are passed with Physical address (DA) matching
the MAC address hash table and with Multicast address without
any conditions.
9
Perfect with
Multicast address
passed
1
0
1
All Rx frames are passed with Physical address (DA) matching
the MAC address and with Multicast address without any
conditions.
10
Hash only with
Physical address
passed
1
0
1
0
All Rx frames are passed with Multicast address matching the
MAC address hash table and with Physical address without any
conditions.
11
Perfect with
Physical address
passed
1
0
1
All Rx frames are passed with Multicast address matching the
MAC address and with Physical address without any conditions.
Note 1: Bit 0 (RX Enable), Bit 5 (RX Unicast Enable) and Bit 6 (RX Multicast Enable) must set to 1 in RXCR1 register.
Note 2: The KSZ8851SNL will discard frame with SA same as the MAC address if bit[0] is set in RXCR2 register.
Table 3. Address Filtering Scheme
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KSZ8851SNLTR | 制造商:Micrel Inc 功能描述: |
| KSZ8851SNL-TR | 功能描述:Ethernet Controller 10/100 Base-T/TX PHY SPI Interface 32-MLF? (5x5) 制造商:microchip technology 系列:- 包裝:剪切帶（CT） 零件狀態(tài):有效 協(xié)議:以太網(wǎng) 功能:控制器 接口:SPI 標(biāo)準(zhǔn):10/100 Base-T/TX PHY 電壓 - 電源:1.8V，2.5V，3.3V 電流 - 電源:- 工作溫度:0°C ~ 70°C 封裝/外殼:32-VFQFN 裸露焊盤，32-MLF? 供應(yīng)商器件封裝:32-MLF?（5x5） 標(biāo)準(zhǔn)包裝:1 |
| KSZ8852HLE-EVAL | 功能描述:KSZ8852HLE - Interface, Ethernet Control Evaluation Board 制造商:microchip technology 系列:- 零件狀態(tài):有效 主要用途:接口，以太網(wǎng)控制 嵌入式:否 使用的 IC/零件:KSZ8852HLE 主要屬性:- 輔助屬性:- 所含物品:板 標(biāo)準(zhǔn)包裝:1 |
| KSZ8852HLEWA | 功能描述:Ethernet Switch 10/100 Base-FX/T/TX PHY Ethernet Interface 64-LQFP (10x10) 制造商:microchip technology 系列:- 包裝:托盤 零件狀態(tài):有效 協(xié)議:以太網(wǎng) 功能:開關(guān) 接口:以太網(wǎng) 標(biāo)準(zhǔn):10/100 Base-FX/T/TX PHY 電壓 - 電源:3.3V 電流 - 電源:- 工作溫度:-40°C ~ 115°C 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商器件封裝:64-LQFP（10x10） 標(biāo)準(zhǔn)包裝:160 |
| KSZ8852HLEYA | 功能描述:Ethernet Switch 10/100 Base-FX/T/TX PHY Ethernet Interface 64-LQFP (10x10) 制造商:microchip technology 系列:- 包裝:托盤 零件狀態(tài):有效 協(xié)議:以太網(wǎng) 功能:開關(guān) 接口:以太網(wǎng) 標(biāo)準(zhǔn):10/100 Base-FX/T/TX PHY 電壓 - 電源:3.3V 電流 - 電源:- 工作溫度:-40°C ~ 115°C 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商器件封裝:64-LQFP（10x10） 標(biāo)準(zhǔn)包裝:160 |
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