參數(shù)資料
型號: KSZ8851SNLI TR
廠商: Micrel Inc
文件頁數(shù): 53/80頁
文件大?。?/td> 0K
描述: IC ETHERNET CTLR 1PORT PCI 32MLF
標(biāo)準(zhǔn)包裝: 1
控制器類型: 以太網(wǎng)控制器,MAC/PHY
接口: 總線
電源電壓: 1.8V,2.5V,3.3V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤,32-MLF?
供應(yīng)商設(shè)備封裝: 32-MLF?(5x5)
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面: 1081 (CN2011-ZH PDF)
其它名稱: 576-3506-6
Micrel, Inc.
KSZ8851SNL/SNLI
August 2009
57
M9999-083109-2.0
Bit
Default Value
R/W
Description
6
0x0
RO
(W1C)
TXSAIS Transmit Space Available Interrupt Status
When this bit is set, it indicates that Transmit memory space available status has
occurred.
When this bit is reset, the Transmit memory space available interrupt is disabled.
5
0x0
RO
RXWFDIS Receive Wakeup Frame Detect Interrupt Status
When this bit is set, it indicates that Receive wakeup frame detect status has occurred.
Write “1000” to PMECR[5:2] to clear this bit
4
0x0
RO
RXMPDIS Receive Magic Packet Detect Interrupt Status
When this bit is set, it indicates that Receive magic packet detect status has occurred.
Write “0100” to PMECR[5:2] to clear this bit.
3
0x0
RO
LDIS Linkup Detect Interrupt Status
When this bit is set, it indicates that wake-up from linkup detect status has occurred.
Write “0010” to PMECR[5:2] to clear this bit.
2
0x0
RO
EDIS Energy Detect Interrupt Status
When this bit is set and bit 2=1, bit 0=0 in IER register, it indicates that wake-up from
energy detect status has occurred. When this bit is set and bit 2, 0=1 in IER register, it
indicates that wake-up from delay energy detect status has occurred.
Write “0001” to PMECR[5:2] to clear this bit.
1
0x0
RO
(W1C)
SPIBEIS SPI Bus Error Interrupt Status
When this bit is set, it indicates that SPI bus error status has occurred.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
0
0x0
RO
Reserved
0x94 – 0x9B: Reserved
RX Frame Count & Threshold Register (0x9C – 0x9D): RXFCTR
This register indicates the current total amount of received frame count in RXQ frame buffer and also is used to program
the received frame count threshold.
Bit
Default Value
R/W
Description
15-8
0x00
RO
RXFC RX Frame Count
To indicate the total received frames in RXQ frame buffer when receive interrupt (bit13=1
in ISR) occurred and write “1” to clear this bit 13 in ISR. The host CPU can start to read
the updated receive frame header information in RXFHSR/RXFHBCR registers after read
this RX frame count register.
7-0
0x00
RW
RXFCT Receive Frame Count Threshold
To program received frame count threshold value.
When bit 5 set to 1 in RXQCR register, the KSZ8851SNL will set RX interrupt (bit 13 in
ISR) when the number of received frames in RXQ buffer exceeds the threshold set in this
register.
TX Next Total Frames Size Register (0x9E – 0x9F): TXNTFSR
This register is used by the host CPU to program the total amount of TXQ buffer space requested for the next transmit.
Bit
Default Value
R/W
Description
15-0
0x0000
RW
TXNTFS TX Next Total Frames Size
The host CPU is used to program the total amount of TXQ buffer space which is required
for next total transmit frames size in double-word count.
When bit 1 (TXQ memory available monitor) is set to 1 in TXQCR register, the
KSZ8851SNL will generate interrupt (bit 6 in ISR register) to CPU when TXQ memory is
available based upon the total amount of TXQ space requested by CPU at this register.
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