參數(shù)資料
型號(hào)： KSZ8851SNLI TR
廠商： Micrel Inc
文件頁(yè)數(shù)： 15/80頁(yè)
文件大?。?/td> 0K
描述： IC ETHERNET CTLR 1PORT PCI 32MLF
標(biāo)準(zhǔn)包裝： 1
控制器類型： 以太網(wǎng)控制器，MAC/PHY
接口： 總線
電源電壓： 1.8V，2.5V，3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤，32-MLF?
供應(yīng)商設(shè)備封裝： 32-MLF?（5x5）
包裝： 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁(yè)面： 1081 (CN2011-ZH PDF)
其它名稱： 576-3506-6
Micrel, Inc.
KSZ8851SNL/SNLI
August 2009
22
M9999-083109-2.0
Clock Generator
The X1 and X2 pins are connected to a 25MHz crystal. X1 can also serve as the connector to a 3.3V, 25MHz oscillator
(as described in the pin description).
Serial Peripheral Interface (SPI)
The KSZ8851SNL supports a SPI interface in slave mode. In this mode, a external SPI master device (micro-controller or
CPU) supplies the operating serial clock (SCLK), chip select (CSN) and serial input data (SI) which is clocked in on the
rising edge of SCLK to KSZ8851SNL device. Serial output data (SO) is driven out by the KSZ8851SNL on the falling edge
of SCLK to external SPI master device. The falling edge of CSN is starting the SPI operation and the rising edge of CSN
is ending the SPI operation. The SCLK stays low state when SPI operation is idle. Figure 6 shows the SPI interface
connection for KSZ8851SNL.
Figure 6. SPI Interface to KSZ8851SNL
There are four SPI operations depending on the opcode inside the command phase:
Internal I/O registers read (opcode = 00)
Internal I/O registers write (opcode = 01)
RXQ FIFO read to receive packet (opcode = 10)
TXQ FIFO write to transmit packet (opcode = 11)
As shown in Table 4 and 5, there are two phases in each SPI operation, the first is command phase and the following is
data phase. Command phase is two bytes long for internal I/O registers access and one byte long for TXQ/RXQ FIFOs
access. Data phase on internal I/O registers access is in the range of one to four bytes long depending on the specified
byte enable bits B[3:0] in command phase, and data phase on TXQ or RXQ FIFOs access is limited up to 6 Kbytes for
TXQ access or 12 Kbytes for RXQ access.
Command Phase (SI pin)
Byte 0 [7:0]
Byte 1 [7:0]
SPI
Operation
Opcode Byte enable
Register Address
Don’t care bits
Data Phase
(SO or SI pins)
Internal I/O
Register Read
0 0
B3 B2 B1 B0 A7 A6 A5 A4 A3 A2
X X X X
1 to 4 Bytes
(read data on SO pin)
Internal I/O
Register Write
0 1
B3 B2 B1 B0 A7 A6 A5 A4 A3 A2
X X X X
1 to 4 Bytes
(write data on SI pin)
Note: In Command phase, A[7:2] access register address location in double word and B[3:0] enable which byte to
access during read or write. In Data phase, the byte 0 is first in/out and byte 3 is last in/out during read or write.
B[3:0] -> 1: enable byte, 0: disable byte.
Table 4. SPI Operation for Registers Access
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參數(shù)描述
KSZ8851SNLTR 制造商:Micrel Inc 功能描述:
KSZ8851SNL-TR 功能描述:Ethernet Controller 10/100 Base-T/TX PHY SPI Interface 32-MLF? (5x5) 制造商:microchip technology 系列:- 包裝:剪切帶（CT） 零件狀態(tài):有效 協(xié)議:以太網(wǎng) 功能:控制器 接口:SPI 標(biāo)準(zhǔn):10/100 Base-T/TX PHY 電壓 - 電源:1.8V，2.5V，3.3V 電流 - 電源:- 工作溫度:0°C ~ 70°C 封裝/外殼:32-VFQFN 裸露焊盤，32-MLF? 供應(yīng)商器件封裝:32-MLF?（5x5） 標(biāo)準(zhǔn)包裝:1
KSZ8852HLE-EVAL 功能描述:KSZ8852HLE - Interface, Ethernet Control Evaluation Board 制造商:microchip technology 系列:- 零件狀態(tài):有效 主要用途:接口，以太網(wǎng)控制 嵌入式:否 使用的 IC/零件:KSZ8852HLE 主要屬性:- 輔助屬性:- 所含物品:板 標(biāo)準(zhǔn)包裝:1
KSZ8852HLEWA 功能描述:Ethernet Switch 10/100 Base-FX/T/TX PHY Ethernet Interface 64-LQFP (10x10) 制造商:microchip technology 系列:- 包裝:托盤 零件狀態(tài):有效 協(xié)議:以太網(wǎng) 功能:開(kāi)關(guān) 接口:以太網(wǎng) 標(biāo)準(zhǔn):10/100 Base-FX/T/TX PHY 電壓 - 電源:3.3V 電流 - 電源:- 工作溫度:-40°C ~ 115°C 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商器件封裝:64-LQFP（10x10） 標(biāo)準(zhǔn)包裝:160
KSZ8852HLEYA 功能描述:Ethernet Switch 10/100 Base-FX/T/TX PHY Ethernet Interface 64-LQFP (10x10) 制造商:microchip technology 系列:- 包裝:托盤 零件狀態(tài):有效 協(xié)議:以太網(wǎng) 功能:開(kāi)關(guān) 接口:以太網(wǎng) 標(biāo)準(zhǔn):10/100 Base-FX/T/TX PHY 電壓 - 電源:3.3V 電流 - 電源:- 工作溫度:-40°C ~ 115°C 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商器件封裝:64-LQFP（10x10） 標(biāo)準(zhǔn)包裝:160
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