參數(shù)資料
型號(hào): KSZ8851SNLI TR
廠商: Micrel Inc
文件頁數(shù): 49/80頁
文件大?。?/td> 0K
描述: IC ETHERNET CTLR 1PORT PCI 32MLF
標(biāo)準(zhǔn)包裝: 1
控制器類型: 以太網(wǎng)控制器,MAC/PHY
接口: 總線
電源電壓: 1.8V,2.5V,3.3V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤,32-MLF?
供應(yīng)商設(shè)備封裝: 32-MLF?(5x5)
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面: 1081 (CN2011-ZH PDF)
其它名稱: 576-3506-6
Micrel, Inc.
KSZ8851SNL/SNLI
August 2009
53
M9999-083109-2.0
RXQ Command Register (0x82 – 0x83): RXQCR
This register is programmed by the Host CPU to issue DMA read or write command to the RXQ and TXQ. This register
also is used to control all RX thresholds enable and status.
Bit
Default Value
R/W
Description
15-13
-
RW
Reserved
12
-
RO
RXDTTS RX Duration Timer Threshold Status
When this bit is set, it indicates that RX interrupt is due to the time start at first received
frame in RXQ buffer exceeds the threshold set in RX Duration Timer Threshold Register
(0x8C, RXDTT).
This bit will be updated when write 1 to bit 13 in ISR register.
11
-
RO
RXDBCTS RX Data Byte Count Threshold Status
When this bit is set, it indicates that RX interrupt is due to the number of received bytes in
RXQ buffer exceeds the threshold set in RX Data Byte Count Threshold Register (0x8E,
RXDBCT).
This bit will be updated when write 1 to bit 13 in ISR register.
10
-
RO
RXFCTS RX Frame Count Threshold Status
When this bit is set, it indicates that RX interrupt is due to the number of received frames
in RXQ buffer exceeds the threshold set in RX Frame Count Threshold Register (0x9C,
RXFCT).
This bit will be updated when write 1 to bit 13 in ISR register.
9
0x0
RW
RXIPHTOE RX IP Header Two-Byte Offset Enable
When this bit is written as 1, the KSZ8851SNL will enable to add two bytes before frame
header in order for IP header inside the frame contents to be aligned with double word
boundary to speed up software operation.
8
-
RW
Reserved
7
0x0
RW
RXDTTE RX Duration Timer Threshold Enable
When this bit is written as 1, the KSZ8851SNL will enable RX interrupt (bit 13 in ISR)
when the time start at first received frame in RXQ buffer exceeds the threshold set in RX
Duration Timer Threshold Register (0x8C, RXDTT).
6
0x0
RW
RXDBCTE RX Data Byte Count Threshold Enable
When this bit is written as 1, the KSZ8851SNL will enable RX interrupt (bit 13 in ISR)
when the number of received bytes in RXQ buffer exceeds the threshold set in RX Data
Byte Count Threshold Register (0x8E, RXDBCT).
5
0x0
RW
RXFCTE RX Frame Count Threshold Enable
When this bit is written as 1, the KSZ8851SNL will enable RX interrupt (bit 13 in ISR)
when the number of received frames in RXQ buffer exceeds the threshold set in RX
Frame Count Threshold Register (0x9C, RXFCT).
4
0x0
RW
ADRFE Auto-Dequeue RXQ Frame Enable
When this bit is written as 1, the KSZ8851SNL will automatically enable RXQ frame buffer
dequeue. The read pointer in RXQ frame buffer will be automatically adjusted to next
received frame location after current frame is completely read by the host.
3
0x0
WO
SDA Start DMA Access
When this bit is written as 1, the KSZ8851SNL allows a DMA operation from the host
CPU to access either read RXQ frame buffer or write TXQ frame buffer with SPI
command operation for RXQ/TXQ FIFO read/write (see Table 5). All registers access are
disabled except this register during this DMA operation.
This bit must be set to 0 when DMA operation is finished in order to access the rest of
registers.
2-1
-
RW
Reserved
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