- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄359083 > M58MR032C (意法半導(dǎo)體) 32 Mbit 2Mb x16, Mux I/O, Dual Bank, Burst 1.8V Supply Flash Memory PDF資料下載
參數(shù)資料
| 型號： | M58MR032C |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 32 Mbit 2Mb x16, Mux I/O, Dual Bank, Burst 1.8V Supply Flash Memory |
| 中文描述： | 32兆位的2Mb x16插槽，復(fù)用的I / O，雙行，突發(fā)1.8V電源快閃記憶體 |
| 文件頁數(shù)： | 13/52頁 |
| 文件大小： | 396K |
| 代理商： | M58MR032C |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁當(dāng)前第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁
13/52
M58MR032C, M58MR032D
CFI Query (RCFI)
The CFI Query Mode is associated to bank A. The
address of the first write cycle must be within the
bank A. The status of the other bank is not affected
by the command (see Table 8). Writing 98h the de-
vice enters the Common Flash Interface Query
mode. Next read operations in the bank A will read
the CFI data. Write a read instruction to return to
Read mode (refer to the Common Flash Interface
section).
Clear Status Register (CLSR)
The Clear Status Register uses a single write op-
eration, which resets bits b1, b3, b4 e b5 of the sta-
tus register. The Clear Status Register is executed
writing the command 50h independently of the ap-
plied V
PP
voltage. After executing this command
the device returns to read array mode. The Clear
Status Register command clears only the status
register of the addressed bank.
Block Erase (EE)
Block erasure sets all the bits within the selected
block to ’1’. One block at a time can be erased. It
is not necessary to pre-program the block as the
P/E.C. will do it automatically before erasing. This
instruction use two writes cycles. The first com-
mand written is the Block Erase Set up command
20h. The second command is the Erase Confirm
command D0h. An address within the block to be
erased should be given to the memory during the
two cycles command. If the second command giv-
en is not an erase confirm, the status register bits
b4 and b5 are set and the instruction aborts.
After writing the command, the device outputs sta-
tus register data when any address within the bank
is read. At the end of the operation the bank will re-
main in read status register until a read array com-
mand is written.
Status Register bit b7 is ’0’ while the erasure is in
progress and ’1’ when it has completed. After com-
pletion the Status Register bit b5 returns ’1’ if there
has been an Erase Failure. Status register bit b1
returns ’1’ if the user is attempting to erase a pro-
tected block. Status Register bit b3 returns a ’1’ if
V
PP
is below V
PPLK
. Erase aborts if RP turns to
V
IL
. As data integrity cannot be guaranteed when
the erase operation is aborted, the erase must be
repeated (see Table 12). A Clear Status Register
instruction must be issued to reset b1, b3, b4 and
b5 of the Status Register. During the execution of
the erase by the P/E.C., the bank with the block in
erase accepts only the RSR (Read Status Regis-
ter) and PES (Program/Erase Suspend) instruc-
tions. See figure 19 for Erase Flowchart and
Pseudo Code.
Bank Erase (BE)
Bank erase sets all the bits within the selected
bank to ’1’. It is not necessary to pre-program the
block as the P/E.C. will do it automatically before
erasing.
This instruction uses two writes cycles. The first
command written is the Bank Erase set-up com-
mand 80h. The second command is the Erase
Confirm command D0h. An address within the
bank to be erased should be given to the memory
during the two cycles command. See the Block
Erase command section for status register bit de-
tails.
Note: 1. First cycle command address should be the same as the operation’s target address. The first cycle of the RD, RSR, RSIG or RCFI
instruction is followed by read operations in the bank array or special register. Any number of read cycles can occur after one com-
mand cycle.
2. BKA means Address within the bank;
BA means Block Address;
EA means Electronic Signature Address;
CA means Common Flash Interface Address;
WA means Word Address;
PA means Protection Register Address (see Table 7);
LPA means Lock Protection Register Address (see Table 7);
RCA means Read Configuration Register Address.
3. PD means Protection Data;
CD means Common Flash Interface Data;
ED means Electronic Signature Data;
WD means Data to be programmed at the address location WA;
LPD means Lock protection Register Data
4. WA1, WA2, WA3 and WA4 must be consecutive address differing only for address bits A1-A0.
5. Read cycle after e CLSR instruction will output the memory array.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M58WR032F-ZBF | CAP 560PF 100V 1% NP0(C0G) AXIAL RAD.20 BULK R-MIL-PRF-20 STANDOFF |
| M58WR032F-ZBE | 32 Mbit (2Mb x 16, Multiple Bank, Burst) 1.8V Supply Flash Memory |
| M58WR032FB80ZB6T | 32 Mbit (2Mb x 16, Multiple Bank, Burst) 1.8V Supply Flash Memory |
| M58WR032FT | 32 Mbit (2Mb x 16, Multiple Bank, Burst) 1.8V Supply Flash Memory |
| M58WR032FT60ZB6 | 32 Mbit (2Mb x 16, Multiple Bank, Burst) 1.8V Supply Flash Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M58MR032C100ZC6T | 功能描述:閃存 32M (2Mx16) 100ns RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲(chǔ)類型:Flash 存儲(chǔ)容量:2 MB 結(jié)構(gòu):256 K x 8 定時(shí)類型: 接口類型:SPI 訪問時(shí)間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| M58MR032C120ZC6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:32 Mbit 2Mb x16, Mux I/O, Dual Bank, Burst 1.8V Supply Flash Memory |
| M58MR032CZC | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:32 Mbit 2Mb x16, Mux I/O, Dual Bank, Burst 1.8V Supply Flash Memory |
| M58MR032D | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:32 Mbit 2Mb x16, Mux I/O, Dual Bank, Burst 1.8V Supply Flash Memory |
| M58MR032D100ZC6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:32 Mbit 2Mb x16, Mux I/O, Dual Bank, Burst 1.8V Supply Flash Memory |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。