參數(shù)資料
型號： M58MR032C
廠商： 意法半導體
英文描述： 32 Mbit 2Mb x16, Mux I/O, Dual Bank, Burst 1.8V Supply Flash Memory
中文描述： 32兆位的2Mb x16插槽，復用的I / O，雙行，突發(fā)1.8V電源快閃記憶體
文件頁數(shù)： 24/52頁
文件大小： 396K
代理商： M58MR032C
M58MR032C, M58MR032D
24/52
COMMON FLASH INTERFACE (CFI)
The Common Flash Interface (CFI) specification is
a JEDEC approved, standardized data structure
that can be read from the Flash memory device.
CFI allows a system software to query the flash
device to determine various electrical and timing
parameters, density information and functions
supported by the device. CFI allows the system to
easily interface to the Flash memory, to learn
about its features and parameters, enabling the
software to configure itself when necessary.
Tables 17, 18, 19, 20, 21, 22 and 23 show the ad-
dress used to retrieve each data. The CFI data
structure gives information on the device, such as
the sectorization, the command set and some
electrical specifications. The CFI data structure
contains also a security area; in this section, a 64
bit unique security number is written, starting at
address 81h. This area can be accessed only in
read mode and there are no ways of changing the
code after it has been written by ST. Write a read
instruction to return to Read mode (see Table 11).
Refer to the CFI Query instruction to understand
how the M58MR032 enters the CFI Query mode.
Table 17. Query Structure Overview
Offset
Note: The Flash memory display the CFI data structure when CFI Query command is issued. In this table are listed the main sub-sections
detailed in Tables 18, 19, 20, 21, 22 and 23. Query data are always presented on the lowest order data outputs.
Table 18. CFI Query Identification String
Offset
Sub-section Name
00h
0020h
88DAh
88DBh
02h
reserved
Note: Query data are always presented on the lowest - order data outputs (ADQ0-ADQ7) only. ADQ8-ADQ15
are ‘0’.
1. DRC means Die Revision Code.
Sub-section Name
Description
00h
Reserved
Reserved for algorithm-specific information
10h
CFI Query Identification String
Command set ID and algorithm data offset
1Bh
System Interface Information
Device timing & voltage information
27h
Device Geometry Definition
Flash device layout
P
Primary Algorithm-specific Extended Query table
Additional information specific to the Primary
Algorithm (optional)
A
Alternate Algorithm-specific Extended Query table
Additional information specific to the Alternate
Algorithm (optional)
80h
Security Code Area
Lock Protection Register
Unique device Number and
User Programmable OTP
Description
Value
ST
Top
Bottom
Manufacturer Code
01h
Device Code
Reserved
03h
DRC
(1)
reserved
0051h
0052h
0059h
0002h
0000h
Die Revision Code
04h-0Fh
10h
11h
12h
13h
14h
15h
16h
17h
Reserved
Query Unique ASCII String "QRY"
"Q"
"R"
"Y"
Primary Algorithm Command Set and Control Interface ID code 16
bit ID code defining a specific algorithm
offset = P = 0039h
0000h
0000h
Address for Primary Algorithm extended Query table (see Table 20)
p = 39h
Alternate Vendor Command Set and Control Interface ID Code
second vendor - specified algorithm supported (note: 0000h means
none exists)
NA
18h
0000h
19h
1Ah
value = A = 0000h
0000h
Address for Alternate Algorithm extended Query table
(0000h means none exists)
NA
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