參數(shù)資料
型號: M58MR032C
廠商: 意法半導(dǎo)體
英文描述: 32 Mbit 2Mb x16, Mux I/O, Dual Bank, Burst 1.8V Supply Flash Memory
中文描述: 32兆位的2Mb x16插槽,復(fù)用的I / O,雙行,突發(fā)1.8V電源快閃記憶體
文件頁數(shù): 17/52頁
文件大?。?/td> 396K
代理商: M58MR032C
17/52
M58MR032C, M58MR032D
operations output the status register after the
erase is resumed. Block erase cannot resume until
program operations initiated during block erase
suspend have completed. It is also possible to
nest suspends as follows: suspend erase in the
first partition, start programming in the second or
in the same partition, suspend programming and
then read from the second or the same partition.
The suggested flowchart for erase suspend/re-
sume features of the memory is shown from Fig-
ure 20.
Program Suspend/Resume (PES/PER)
Program suspend is accepted only during the Pro-
gram instruction execution. When a Program Sus-
pend command is written to the C.I., the P/E.C.
freezes the Program operation.
Program Resume (PER) continues the Program
operation. Program Suspend (PES) consists of
writing the command B0h and the address should
be within the bank with the word in programming
(see Table 11).
The Status Register bit b2 is set to '1' (within 5μs)
when the program has been suspended. Bit b2 is
set to '0' in case the program is completed or in
progress (see Table 12).
The valid commands while program is suspended
are: Program/Erase Resume, Read Array, Read
Status Register, Read Electronic Signature, CFI
Query. During program suspend mode, the device
goes in standby mode by taking E to V
IH
. This re-
duces active current consumption. Program is
aborted if RP turns to V
IL
.
If a Program Suspend instruction was previously
executed, the Program operation may be resumed
by issuing the command D0h using an address
within the suspended bank (see Table 11). The
status register bit b2 and bit b7 are cleared when
program resumes and read operations output the
status register after the erase is resumed (see Ta-
ble 12). The suggested flowchart for program sus-
pend/resume features of the memory is shown
from Figure 18.
Block Protect (BP)
The BP instruction use two write cycles. The first
command written is the protection set-up 60h. The
second command is block Protect command 01h,
written to an address within the block to be protect-
ed (see Table 11). If the second command is not
recognized by the C.I the bit 4 and bit 5 of the sta-
tus register will be set to indicate a wrong se-
quence of commands (see Table 12). To read the
status register write the RSR command.
Block Unprotect (BU)
The instruction use two write cycles. The first com-
mand written is the protection set-up 60h. The sec-
ond command is block Unprotect command D0h,
written to an address within the block to be protect-
ed (see Table 11). If the second command is not
recognized by the C.I the bit 4 and bit 5 of the sta-
tus register will be set to indicate a wrong se-
quence of commands (see Table 12). To read the
status register write the RSR command.
Block Lock (BL)
The instruction use two write cycles. The first com-
mand written is the protection set-up 60h. The sec-
ond command is block Lock command 2Fh,
written to an address within the block to be protect-
ed (see Table 11). If the second command is not
recognized by the C.I the bit 4 and bit 5 of the sta-
tus register will be set to indicate a wrong se-
quence of commands. To read the status register
write the RSR command (see Table 12).
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