Introduction
MOTOROLA
MC68307 USER’S MANUAL
1-5
and memory system. The SIM07 provides programmable circuits to perform address-decod-
ing and chip selects, wait-state insertion, interrupt handling, clock generation, discrete I/O,
and power management features.
1.2.2.1 EXTERNAL BUS INTERFACE. The external bus interface (EBI) handles the trans-
fer of information between the internal EC000 core and memory, peripherals, or other pro-
cessing elements in the external address space. It consists of an M68000 bus interface and
an 8051-compatible bus interface. The external M68000 bus provides up to 24 address lines
and 16 data lines. Each bus access can appear externally either as an M68000 bus cycle
(either 16-bit or 8-bit dynamic data bus width) or an 8-bit wide 8051-compatible bus cycle
(multiplexing address and 8-bit data) with the respective sets of control signals. The default
bus cycle is an M68000 16-bit-wide one, the 8051-compatible address space being pro-
grammable.
1.2.2.2 CHIP SELECT AND WAIT STATE GENERATION. Four programmable chip select
outputs provide signals to enable external memory and peripheral circuits, providing all
handshaking and timing signals for automatic wait-state insertion and data bus sizing.
Base memory address and block size are both programmable, with some restrictions, (e.g.
a starting address must be on a boundary which is a multiple of the block size). Each chip-
select is general-purpose. However one of the chip-selects can be programmed to select an
addressing range which is decoded as an 8051-compatible bus access, and another can be
used to enable one of four simple external peripherals. Data bus width (8-bit or 16-bit) is pro-
grammable on all four chip-selects and further decoding is available for protection from user
mode access or read-only access.
tion registers that allow general system functions to be controlled and monitored. For exam-
ple, all on-chip registers can be relocated as a block by programming a module base
address, power-down modes can be selected, and the source of the most recent RESET or
BERR can be checked. The hardware watchdog features can be enabled or disabled and
the bus timeout times can be programmed.
The power-down mode allows software to disable the EC000 core during periods of inactiv-
ity. This feature works in conjunction with the interrupt control logic to allow any interrupt
condition to cause a wake-up, which causes the EC000 core to resume processing without
requiring any RESET or re-initialization. All register contents are preserved, and the inter-
rupt which caused wake-up is serviced in the normal manner as soon as the clock restarts.
To reduce power consumption further, the internal clocks to the on-chip peripheral modules
can be disabled by software.
1.2.2.4 PARALLEL INPUT/OUTPUT PORTS. Two general-purpose ports (A and B) are
provided for input/output, although the pins for these ports are shared with other functions.
Some bits in port A are multiplexed with the peripheral chip-select lines and timer output sig-
nals, and port B is multiplexed with various peripheral I/O lines from the UART, M-Bus and
Timer modules. Maximum flexibility is therefore available for differing hardware configura-
tions. Eight of the 16 Port B lines are also latched inputs to the interrupt controller, with pro-
grammable interrupt priority level.