System Integration Module
5-38
MC68307 USER’S MANUAL
MOTOROLA
figured as dedicated inputs/outputs for on-chip peripherals returns the current state of the
pin, whether it is an input or an output.
1 = The corresponding Port B bit (input or output) currently holds a logic 1 (high) value
(read cycle) OR a logic 1 is to be stored to that bit (write cycle).
0 = The corresponding Port B bit (input or output) currently holds a logic 0 (low) value
(read cycle) OR a logic 0 is to be stored to that bit (write cycle).
5.2.4 Interrupt Control Registers
The following paragraphs describe the interrupt control registers.
5.2.4.1 LATCHED INTERRUPT CONTROL REGISTERS 1,2 (LICR1,LICR2). These reg-
isters control the interrupt priorities for the external general-purpose latched interrupt input
signals, and also allow software to reset any pending interrupts from these lines. There are
eight general-purpose latched interrupt inputs altogether, each has four bits assigned to it in
these registers. The registers can be read or written at any time. When read, the data re-
turned is the last value that was written to the register, with the exception of the reset bits,
which are transitory functions. The registers can be accessed by either word (16-bit) or byte
(8-bit) data transfer instructions. An 8-bit write to one half of a register leaves the other half
intact.
PIR1–PIR8—Pending Interrupt Reset 1–8
These bits allow the user to clear any pending interrupt on the interrupt input latch for the
specified input (INT1–INT8). The action of writing a logic 1 to one of these bit positions
clears the latch, so that the interrupt input must be toggled before another interrupt is
latched. It is not necessary to subsequently write a logic 0 to 'release' the reset condition,
this is done internally.
When read, these bits indicate the current value of the latched interrupt, a 1 indicating ac-
tive, a zero inactive.
These bits also enable a new value of the IPL field to be set. Each interrupt channel ig-
nores the value written to its INTxIPL(2–0) field UNLESS the corresponding PIRx bit is
LICR1
MBASE+$020
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PIR1
INT1IPL(2–0)
PIR2
INT2IPL(2–0)
PIR3
INT3IPL(2–0)
PIR4
INT4IPL(2–0)
RESET:
1
0
1
0
1
0
1
0
Read/Write
Supervisor or User
LICR2
MBASE+$022
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PIR5
INT5IPL(2–0)
PIR6
INT6IPL(2–0)
PIR7
INT7IPL(2–0)
PIR8
INT8IPL(2–0)
RESET:
1
0
1
0
1
0
1
0
Read/Write
Supervisor or User