System Integration Module
5-6
MC68307 USER’S MANUAL
MOTOROLA
For a given chip select block, the user may also choose whether the chip select allows read-
only, write-only, or read/write accesses, whether the chip select should match only one
function code value or all values, whether a DTACK is automatically generated for this chip
select and after how many wait states (from zero to six).
5.1.2.1 PROGRAMMABLE DATA-BUS SIZE. Each of the chip selects include the facility of
a data-bus port sizing extension to the basic M68000 bus which allows the system designer
to mix 16-bit and 8-bit contiguous address memory devices (RAM, ROM) on a 16-bit data
bus system. If the EC000 core executes a 16-bit data transfer instruction, then two 8-bit bus
cycles appear, using the external M68000 data bus upper half (D15–D8) only, the least
significant bit of address (A0) incrementing automatically from one to the next. A0 should be
ignored in 16-bit data-bus cycles, even if only the upper or lower byte is being read/written.
Note that a 16-bit data bus is always used internally for access to peripheral registers,
regardless of any mode settings for the external bus. Where peripheral registers are 16-bits
wide, they can be read or written in one bus cycle only, eliminating possible conflicts and
reading of inaccurate values where 16-bit-wide register contents are volatile (timer counter
registers, for example) or where the whole 16-bit value affects some aspect of system
operation (chip select base address, for example).
Where internal peripherals are 8-bits wide, e.g., the MC68681-compatible UART, they are
accessed at every alternate (odd) address. It is recommended that any external peripheral
that needs only an 8-bit data-bus interface but does not require contiguous address
locations, uses a chip select configured as 16-bit data-bus width, and connects to D7–D0.
This balances more evenly the load on the two halves of the data bus in an 8-bit system.
Figure 5-2. Chip-Select Block Diagram
BASE REGISTER 0 (BR0)
COMPARE LOGIC
OPTION REGISTER0 (OR0)
CS0
CS1
CS2
CS3
DTACK GENERATION
R/W
CS1
CS2
CS3
DATA
BUS
ADDRESS
AND
FUNCTION
CODES