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參數(shù)資料
| 型號(hào)： | MC68307FG16 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 16.67 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁(yè)數(shù)： | 21/264頁(yè) |
| 文件大?。?/td> | 949K |
| 代理商： | MC68307FG16 |
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System Integration Module
5-22
MC68307 USER’S MANUAL
MOTOROLA
5.2.1 System Configuration and Protection Registers
Four reserved long-word entries in the M68000 exception vector table (refer to Table 4-5)
are used as addresses for internal system configuration registers. These entries are at
locations $0F0, $0F4, $0F8, and $0FC. The first entry is the on-chip MBAR entry; the
second is the on-chip SCR entry; the third and fourth entries are reserved for future use by
Motorola. Note that some other manufacturers use these reserved locations for other
purposes, for example, a dedicated set of autovector locations for on-chip peripherals. In the
MC68307, this concept is replaced by programmable interrupt vectors, which can use any
spare block of 16 vector locations, except for the reserved ones.
5.2.1.1 MODULE BASE ADDRESS REGISTER (MBAR). The MBAR can be read or
written at any time. It is a 16-bit read-write location, and resides in the exception vector table,
at address hex $0000F2, in supervisor data space. The MBAR cannot be accessed in user
data space. The register consists of the high address bits, the compare function code bit,
and the function code bits, as shown below. The register should only be accessed with Word
size instructions. Upon a total system reset, the MBAR value may be read as $BFFF, but
this value holds no meaning, and therefore the on-chip peripheral locations cannot be
accessed at any address, until the MBAR is written by the user.
FC2–FC0—Function Codes
This field should be initialized to provide the required function code which is used when
the on-chip registers are accessed. The primary function of this field is to allow the user
to select whether or not the block of registers should be accessible in supervisor data
space only (101B) or user data space only (001B). If both are required, then the CFC bit
should be cleared to 0.
NOTE
Do not assign this field to the M68000 core interrupt acknowl-
edge space (FC2–FC0 = 111).
CFC—Compare Function Codes
This bit allows the system configuration logic to determine whether or not the user wishes
to restrict the on-chip peripheral registers to access by one function code alone, as spec-
ified by the FC2–FC0 bits.
0 = The FCx bits in the MBAR are ignored. Accesses to the MC68307 peripheral reg-
isters block occur without comparing the FCx bits.
1 = The FCx bits in the MBAR are compared. The address space compare logic uses
the FCx bits to detect address matches.
MBAR
$0000F2
15
13
12
11
0
FC2–FC0
CFC
BA23–BA12
RESET:
1
0
1
Read/Write
Supervisor only
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| MC68331CPV16B1 | 32-BIT, 16 MHz, MICROCONTROLLER, PQFP144 |
相關(guān)代理商/技術(shù)參數(shù) |
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| MC68322FT20 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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