參數(shù)資料
型號(hào): MC68307FG16
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, 16.67 MHz, MICROCONTROLLER, PQFP100
封裝: PLASTIC, QFP-100
文件頁(yè)數(shù): 36/264頁(yè)
文件大?。?/td> 949K
代理商: MC68307FG16
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System Integration Module
MOTOROLA
MC68307 USER’S MANUAL
5-35
5.2.3.2 PORT A DATA DIRECTION REGISTER (PADDR). This 8-bit read/write register is
used by the user to program the general-purpose I/O lines in port A, the 8-bit I/O port, as
inputs or outputs.
From a cold reset, these register bits are all cleared, configuring all port A I/O lines as
general-purpose inputs. Bootstrap software must write an appropriate value into PADDR if
any of the port A lines are required as outputs. Pullup resistors may be required to solve the
problem of port A I/O lines perhaps floating at cold reset, until PADDR is written. They may
also be required if the peripheral chip select feature (which shares port A pins) is used, as
these signals would otherwise momentarily float at cold reset until configured.
DA7–DA0—Data Direction Field A
These bits are used to determine whether the corresponding port A input/output line are
inputs or latched outputs. As such, the DDR bit for any one port A line is ignored unless
that port A line is configured as general-purpose I/O in the PACNT. If a particular general-
purpose I/O line has its direction changed from an input to an output, the initial data which
appears on that pin is the last data written to the latch by the PADAT register.
0 = The corresponding port A I/O bit is to be an
input.
1 = The corresponding port A I/O bit is to be an
output.
5.2.3.3 PORT A DATA REGISTER (PADAT). This 8-bit read/write register is used by the
user to read or write the logic states of the general-purpose I/O lines in port A, the 8-bit I/O
port.
From a cold reset, these register bits are all cleared, so when any port A lines are configured
as outputs, a logic zero appears on those pins, unless PADAT is written with an initial data
value to be written.
PA7–PA0—Port A Data Field
If the corresponding port A bit is configured as a general-purpose output in the PADDR
and PACNT, then writing a certain logic value to that bit in the PADAT register enables
that logic level to appear on the output pin. Data written is latched internally, even for pins
PADDR
MBASE+$013
7
0
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
RESET:
0
Read/Write
Supervisor or User
PADAT
MBASE+$015
7
0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
RESET:
0
Read/Write
Supervisor or User
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