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參數(shù)資料
| 型號(hào)： | MC68307FG16 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 16.67 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁(yè)數(shù)： | 77/264頁(yè) |
| 文件大?。?/td> | 949K |
| 代理商： | MC68307FG16 |
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Serial Module
8-8
MC68307 USER’S MANUAL
MOTOROLA
8.3.2.2 RECEIVER. The receiver is enabled through its UCR located within the serial mod-
ule. Functional timing information for the receiver is shown in Figure 8-6. The receiver looks
for a high-to-low (mark-to-space) transition of the start bit on RxD. When a transition is
detected, the state of RxD is sampled each 16
× clock for eight clocks, starting one-half clock
after the transition (asynchronous operation) or at the next rising edge of the bit time clock
(synchronous operation). If RxD is sampled high, the start bit is invalid, and the search for
the valid start bit begins again. If RxD is still low, a valid start bit is assumed, and the receiver
continues to sample the input at one-bit time intervals, at the theoretical center of the bit,
until the proper number of data bits and parity, if any, is assembled and one stop bit is
detected. Data on the RxD input is sampled on the rising edge of the programmed clock
source. The least significant bit is received first. The data is then transferred to a receiver
holding register, and the RxRDY bit in the USR is set. If the character length is less than
eight bits, the most significant unused bits in the receiver holding register are cleared.
After the stop bit is detected, the receiver immediately looks for the next start bit. However,
if a non-zero character is received without a stop bit (framing error) and RxD remains low
for one-half of the bit period after the stop bit is sampled, the receiver operates as if a new
start bit is detected. The parity error (PE), framing error (FE), overrun error (OE), and
received break (RB) conditions (if any) set error and break flags in the USR at the received
character boundary and are valid only when the RxRDY bit in the USR is set.
If a break condition is detected (RxD is low for the entire character including the stop bit), a
character of all zeros is loaded into the receiver holding register, and the RB and RxRDY
bits in the USR are set. The RxD signal must return to a high condition for at least one-half
bit time before a search for the next start bit begins.
The receiver detects the beginning of a break in the middle of a character if the break per-
sists through the next character time. When the break begins in the middle of a character,
the receiver places the damaged character in the receiver first-in-first-out (FIFO) stack and
sets the corresponding error conditions and RxRDY bit in the USR. Then, if the break per-
sists until the next character time, the receiver places an all-zero character into the receiver
FIFO and sets the corresponding RB and RxRDY bits in the USR.
8.3.2.3 FIFO STACK. The FIFO stack is used in the UART's receiver buffer logic. The stack
consists of three receiver holding registers. The receive buffer consists of the FIFO and a
receiver shift register connected to the RxD (refer to Figure 8-4). Data is assembled in the
receiver shift register and loaded into the top empty receiver holding register position of the
FIFO. Thus, data flowing from the receiver to the CPU is quadruple buffered.
In addition to the data byte, three status bits, PE, FE, and RB, are appended to each data
character in the FIFO; OE is not appended. By programming the ERR bit in the channel's
mode register (UMR1), status is provided in character or block modes.
The RxRDY bit in the USR is set whenever one or more characters are available to be read
by the CPU. A read of the receiver buffer produces an output of data from the top of the FIFO
stack. After the read cycle, the data at the top of the FIFO stack and its associated status
bits are 'popped', and new data can be added at the bottom of the stack by the receiver shift
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PDF描述 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68307UM | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Technical Summary Integrated Multiple-Bus Processor |
| MC68307V | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Technical Summary Integrated Multiple-Bus Processor |
| MC68322 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Integrated Printer Processor |
| MC68322AD | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Integrated Printer Processor |
| MC68322FT20 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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