
Serial Module
MOTOROLA
MC68307 USER’S MANUAL
8-15
8.4.1.1 MODE REGISTER 1 (UMR1). UMR1 controls some of the serial module configura-
tion. This register can be read or written at any time. It is accessed when the mode register
pointer points to UMR1. The pointer is set to UMR1 by RESET or by a set pointer command,
using the control register. After reading or writing UMR1, the pointer points to UMR2.
RxRTS—Receiver Request-to-Send Control
1 = Upon receipt of a valid start bit, RTS is negated if the UART's FIFO is full. RTS is
reasserted when the FIFO has an empty position available.
0 = The receiver has no effect on RTS.
This feature can be used for flow control to prevent overrun in the receiver by using the
RTS output to control the CTS input of the transmitting device. If both the receiver and
transmitter are programmed for RTS control, RTS control is disabled for both since this
on programming the transmitter RTS control.
Table 8-1. Serial Module Programming Model
Address
Register Read (R/W = 1)
Register Write (R/W = 0)
MBASE+$101
MODE REGISTER (UMR1, UMR2)
MBASE+$103
STATUS REGISTER (USR)
CLOCK-SELECT REGISTER (UCSR)
MBASE+$105
DO NOT ACCESS1
COMMAND REGISTER (UCR)
MBASE+$107
RECEIVER BUFFER (URB)
TRANSMITTER BUFFER (UTB)
MBASE+$109
INPUT PORT CHANGE REGISTER (UIPCR)
AUXILIARY CONTROL REGISTER (UACR)
MBASE+$10B
INTERRUPT STATUS REGISTER (UISR)
INTERRUPT MASK REGISTER (UIMR)
MBASE+$10D
BAUD RATE GENERATOR PRESCALE MSB (UBG1)
MBASE+$10F
BAUD RATE GENERATOR PRESCALE LSB (UBG2)
DO NOT ACCESS1
MBASE+$119
INTERRUPT VECTOR REGISTER (UIVR)
MBASE+$11B
INPUT PORT REGISTER (UIP)
DO NOT ACCESS1
MBASE+$11D
DO NOT ACCESS1
OUTPUT PORT BIT SET CMD (UOP1)2
MBASE+$11F
DO NOT ACCESS1
OUTPUT PORT BIT RESET CMD (UOP0)2
NOTES
1. This address is used for factory testing and should not be read. Reading this location results in undesired effects and
possible incorrect transmission or reception of characters. Register contents may also be changed.
2. Address-triggered commands.
UMR1
MBASE + $101
7
6
5
4
3
2
1
0
RxRTS
RxIRQ
ERR
PM1
PM0
PT
B/C1
B/C0
RESET:
0
Read/Write
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