MOTOROLA
CONFIGURABLE TIMER MODULE 4
MC68336/376
10-6
USER’S MANUAL
10.6.1 FCSM Counter
The FCSM counter consists of a 16-bit register and a 16-bit up-counter. Reading the
register transfers the contents of the counter to the data bus, while a write to the
register loads the counter with a new value. Overflow of the counter is defined to be
the transition from $FFFF to $0000. An overflow condition sets the counter overflow
flag (COF) in the FCSM status/interrupt/control register (FCSMSIC).
NOTE
Reset presets the counter register to $0000. Writing $0000 to the
counter register while the counter’s value is $FFFF does not set the
COF flag and does not generate an interrupt request.
10.6.2 FCSM Clock Sources
The FCSM has eight software selectable counter clock sources, including:
Six CPSM prescaler outputs (PCLK[1:6])
Rising edge on CTM2C input
Falling edge on the CTM2C input
The clock source is selected by the CLK[2:0] bits in FCSMSIC. When the CLK[2:0] bits
are being changed, internal circuitry guarantees that spurious edges occurring on the
CTM2C pin do not affect the FCSM. The read-only IN bit in FCSMSIC reflects the state
of CTM2C. This pin is Schmitt-triggered and is synchronized with the system clock.
The maximum allowable frequency for a clock input on CTM2C is fsys/4.
10.6.3 FCSM External Event Counting
When an external clock source is selected, the FCSM can act as an event counter
simply by counting the number of events occurring on the CTM2C input pin. Alterna-
tively, the FCSM can be programmed to generate an interrupt request when a pre-
defined number of events have been counted. This is done by presetting the counter
with the two’s complement value of the desired number of events.
10.6.4 FCSM Time Base Bus Driver
The DRVA and DRVB bits in FCSMSIC select the time base bus to be driven. Which
of the time base buses is driven depends on where the FCSM is physically placed in
information.
WARNING
Two time base buses should not be driven at the same time.
10.6.5 FCSM Interrupts
The FCSM can optionally request an interrupt when its counter overflows and the COF
bit in FCSMSIC is set. To enable interrupts, set the IL[2:0] field in the FCSMSIC to a
non-zero value. The CTM4 compares the CPU32 IP mask value to the priority of the
requested interrupt designated by IL[2:0] to determine whether it should contend for
336376UMBook Page 6 Friday, November 15, 1996 2:09 PM