MOTOROLA
REGISTER SUMMARY
MC68336/376
D-74
USER’S MANUAL
TCR1P[1:0] — Timer Count Register 1 Prescaler Control
TCR1 is clocked from the output of a prescaler. The prescaler's input is the internal
TPU system clock divided by either 4 or 32, depending on the value of the PSCK bit.
The prescaler divides this input by 1, 2, 4, or 8. Channels using TCR1 have the capa-
bility to resolve down to the TPU system clock divided by four. Table D-52 is a sum-
mary of prescaler output.
TCR2P[1:0] — Timer Count Register 2 Prescaler Control
TCR2 is clocked from the output of a prescaler. If T2CG = 0, the input to the TCR2
prescaler is the external TCR2 clock source. If T2CG = 1, the input is the TPU system
clock divided by eight. The TCR2P field specifies the value of the prescaler: 1, 2, 4, or
8. Channels using TCR2 have the capability to resolve down to the TPU system clock
divided by eight. Table D-53 is a summary of prescaler output.
EMU — Emulation Control
In emulation mode, the TPU executes microinstructions from TPURAM exclusively.
Access to the TPURAM module via the IMB is blocked, and the TPURAM module is
dedicated for use by the TPU. After reset, this bit can be written only once.
0 = TPU and TPURAM operate normally.
1 = TPU and TPURAM operate in emulation mode.
T2CG — TCR2 Clock/Gate Control
When T2CG is set, the external TCR2 pin functions as a gate of the DIV8 clock (the
TPU system clock divided by eight). In this case, when the external TCR2 pin is low,
the DIV8 clock is blocked, preventing it from incrementing TCR2. When the external
TCR2 pin is high, TCR2 is incremented at the frequency of the DIV8 clock. When
T2CG is cleared, an external clock input from the TCR2 pin, which has been synchro-
nized and fed through a digital filter, increments TCR2.
0 = TCR2 pin used as clock source for TCR2.
1 = TCR2 pin used as gate of DIV8 clock for TCR2.
Table D-52 TCR1 Prescaler Control Bits
TCR1P[1:0]
Prescaler
Divide By
TCR1 Clock Input
PSCK = 0
PSCK = 1
00
1
fsys ÷ 32
fsys ÷ 4
01
2
fsys ÷ 64
fsys ÷ 8
10
4
fsys ÷ 128
fsys ÷ 16
11
8
fsys ÷ 256
fsys ÷ 32
Table D-53 TCR2 Prescaler Control Bits
TCR2P[1:0]
Prescaler
Divide By
Internal Clock
Divided By
External Clock
Divided By
00
1
8
1
01
2
16
2
10
4
32
4
11
8
64
8
336376UMBook Page 74 Friday, November 15, 1996 2:09 PM