
MOTOROLA
QUEUED SERIAL MODULE
MC68336/376
9-18
USER’S MANUAL
Delay after transfer can be used to provide a peripheral deselect interval. A delay can
also be inserted between consecutive transfers to allow serial A/D converters to com-
plete conversion. Writing a value to DTL[7:0] in SPCR1 specifies a delay period. The
DT bit in each command RAM byte determines whether the standard delay period (DT
= 0) or the specified delay period (DT = 1) is used. The following expression is used
to calculate the delay:
where DTL equals {1, 2, 3,..., 255}.
A zero value for DTL[7:0] causes a delay-after-transfer value of 8192/System Clock.
Adequate delay between transfers must be specified for long data streams because
the QSPI requires time to load a transmit RAM entry for transfer. Receiving devices
need at least the standard delay between successive transfers. If the system clock is
operating at a slower rate, the delay between transfers must be increased proportion-
ately.
Operation is initiated by setting the SPE bit in SPCR1. Shortly after SPE is set, the
QSPI executes the command at the command RAM address pointed to by NEWQP.
Data at the pointer address in transmit RAM is loaded into the data serializer and
transmitted. Data that is simultaneously received is stored at the pointer address in re-
ceive RAM.
When the proper number of bits have been transferred, the QSPI stores the working
queue pointer value in CPTQP, increments the working queue pointer, and loads the
next data for transfer from transmit RAM. The command pointed to by the incremented
working queue pointer is executed next, unless a new value has been written to
NEWQP. If a new queue pointer value is written while a transfer is in progress, that
transfer is completed normally.
When the CONT bit in a command RAM byte is set, PCS pins are continuously driven
in specified states during and between transfers. If the chip-select pattern changes
during or between transfers, the original pattern is driven until execution of the follow-
ing transfer begins. When CONT is cleared, the data in register PORTQS is driven be-
tween transfers. The data in PORTQS must match the inactive states of SCK and any
peripheral chip-selects used.
When the QSPI reaches the end of the queue, it sets the SPIF flag. If the SPIFIE bit
in SPCR2 is set, an interrupt request is generated when SPIF is asserted. At this point,
the QSPI clears SPE and stops unless wrap-around mode is enabled.
Delay after Transfer
32
DTL[7:0]
×
System Clock
------------------------------------
=
Standard Delay after Transfer
17
System Clock
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=
336376UMBook Page 18 Friday, November 15, 1996 2:09 PM