MC68336/376
CAN 2.0B CONTROLLER MODULE (TouCAN)
MOTOROLA
USER’S MANUAL
13-9
13.4.3.1 Configuring the TouCAN Bit Timing
The following considerations must be observed when programming bit timing func-
tions.
If the programmed PRESDIV value results in a single system clock per one time
quantum, then the PSEG2 field in CANCTRL2 register should not be pro-
grammed to zero.
If the programmed PRESDIV value results in a single system clock per one time
quantum, then the information processing time (IPT) equals three time quanta,
otherwise it equals two time quanta. If PSEG2 equals two, then the TouCAN
transmits one time quantum late relative to the scheduled sync segment.
If the prescaler and bit timing control fields are programmed to values that result
in fewer than ten system clock periods per CAN bit time and the CAN bus loading
is 100%, anytime the rising edge of a start-of-frame (SOF) symbol transmitted by
another node occurs during the third bit of the intermission between messages,
the TouCAN may not be able to prepare a message buffer for transmission in time
to begin its own transmission and arbitrate against the message which transmit-
ted the early SOF.
The TouCAN bit time must be programmed to be greater than or equal to nine
system clocks, or correct operation is not guaranteed.
13.4.4 Error Counters
The TouCAN has two error counters, the transmit (TX) error counter and the receive
(RX) error counter. Refer to APPENDIX D REGISTER SUMMARY for more informa-
tion on error counters. The rules for increasing and decreasing these counters are de-
scribed in the CAN protocol, and are fully implemented in the TouCAN. Each counter
has the following features:
8-bit up/down counter
Increment by 8 (RX error counter also increments by one)
Decrement by one
Avoid decrement when equal to zero
RX error counter reset to a value between 119 and 127 inclusive, when the
TouCAN transitions from error passive to error active
Following reset, both counters reset to zero
Detect values for error passive, bus off and error active transitions
Table 13-8 Example System Clock, CAN Bit Rate and S-Clock Frequencies
System Clock
Frequency
(MHz)
CAN Bit-Rate
(MHz)
Possible S-Clock
Frequency (MHz)
Possible Number of
Time Quanta/Bit
PRESDIV Value + 1
25
1
25
1
20
1
10, 20
2, 1
16
1
8, 16
2, 1
25
0.125
1, 1.25, 2.5
8,10, 20
25, 20,10
20
0.125
1, 2, 2.5
8, 16, 20
20, 10, 8
16
0.125
1, 2
8,16
16, 8
336376UMBook Page 9 Friday, November 15, 1996 2:09 PM