MOTOROLA
MC68336/376
xiv
USER’S MANUAL
(Continued)
Paragraph
Title
Page
TABLE OF CONTENTS
D.2.3
Clock Synthesizer Control Register .................................................. D-8
D.2.4
Reset Status Register ...................................................................... D-9
D.2.5
System Integration Test Register (ECLK) ........................................ D-9
D.2.6
Port E Data Register ...................................................................... D-10
D.2.7
Port E Data Direction Register ....................................................... D-10
D.2.8
Port E Pin Assignment Register ..................................................... D-10
D.2.9
Port F Data Register ....................................................................... D-11
D.2.10
Port F Data Direction Register ....................................................... D-11
D.2.11
Port F Pin Assignment Register ..................................................... D-11
D.2.12
System Protection Control Register ............................................... D-12
D.2.13
Periodic Interrupt Control Register ................................................. D-13
D.2.14
Periodic Interrupt Timer Register ................................................... D-14
D.2.15
Software Watchdog Service Register ............................................. D-14
D.2.16
Port C Data Register ...................................................................... D-15
D.2.17
Chip-Select Pin Assignment Registers ........................................... D-15
D.2.18
Chip-Select Base Address Register Boot ROM ............................. D-17
D.2.19
Chip-Select Base Address Registers ............................................. D-17
D.2.20
Chip-Select Option Register Boot ROM ......................................... D-18
D.2.21
Chip-Select Option Registers ......................................................... D-18
D.2.22
Master Shift Registers .................................................................... D-21
D.2.23
Test Module Shift Count Register .................................................. D-21
D.2.24
Test Module Repetition Count Register ......................................... D-21
D.2.25
Test Submodule Control Register .................................................. D-21
D.2.26
Distributed Register ........................................................................ D-21
D.3
Standby RAM Module ............................................................................ D-22
D.3.1
RAM Module Configuration Register .............................................. D-22
D.3.2
RAM Test Register ......................................................................... D-23
D.3.3
Array Base Address Register High ................................................. D-23
D.3.4
Array Base Address Register Low ................................................. D-23
D.4
Masked ROM Module ............................................................................. D-24
D.4.1
Masked ROM Module Configuration Register ................................ D-24
D.4.2
ROM Array Base Address Register High ....................................... D-26
D.4.3
ROM Array Base Address Register Low ........................................ D-26
D.4.4
ROM Signature High Register ........................................................ D-26
D.4.5
ROM Signature Low Register ......................................................... D-26
D.4.6
ROM Bootstrap Words ................................................................... D-27
D.5
QADC Module ........................................................................................ D-28
D.5.1
QADC Module Configuration Register ........................................... D-28
D.5.2
QADC Test Register ....................................................................... D-29
D.5.3
QADC Interrupt Register ................................................................ D-29
D.5.4
Port A/B Data Register ................................................................... D-30
336376UMBook Page xiv Friday, November 15, 1996 2:09 PM