
MC68336/376
MOTOROLA
USER’S MANUAL
I-5
EDGEN D-62
EDGEP D-62
EDIV 5-12, D-8
EDPOL D-65
EMPTY 13-4
EMU 11-5, 11-15, D-74
EMUL D-25
Emulation
control (EMU) 11-15, D-74
mode control (EMUL) D-25
support 11-5
EN D-70
Encoded
one of three channel priority levels (CH) D-80
time function for each channel (CHANNEL) D-78
type of host service (CH) D-79
Ending queue pointer (ENDQP) D-52
End-of-
frame (EOF) 13-16
queue condition 8-30
ENDQP 9-8, D-52
EOF 13-16
ERRINT D-96
ERRMSK D-89
Error
conditions 9-28
counters 13-9
detection circuitry 9-2
interrupt (ERRINT) D-96
interrupt mask (ERRMSK) D-89
ESTAT D-94
ETRIG 8-5
Event flag (FLAG) D-63
Event timing 11-3
Exception
instruction (RTE) 5-36
processing 4-15, 5-40
sequence 4-17
types of exceptions 4-17
vectors 4-15
exception vector assignments 4-16
vector 5-40, 11-6
EXOFF D-6
EXT D-9
Extended message format 13-1
frames 13-4
External
bus
arbitration 5-38
clock
division (EDIV) D-8
division bit (EDIV) 5-12
operation during LPSTOP 5-12
signal (ECLK) 5-12
interface (EBI) 5-19
control signals 5-21
clock input timing diagram A-10
clock off (EXOFF) D-6
digital supply pin 8-6
multiplexing 8-10
reset (EXT) D-9
trigger pins 8-5
Externally
input clock frequency D-14
multiplexed mode (MUX) D-31
EXTRST (external reset) 5-48
–F–
Factory test 5-64
FAR 4-22
Fast
quadrature decode (FQD) 11-12
reference 5-4
circuit 5-5
termination
cycles 5-26, 5-30
read cycle timing diagram A-13
write cycle timing diagram A-14
Fast reference frequency D-14
Fault confinement state (FCS) 13-10, D-95
FC 5-22
FCS 13-10, D-95
FCSM 10-5
block diagram 10-5
clock sources 10-6
counter 10-6
external event counting 10-6
interrupts 10-6
registers 10-7
counter register (FCSMCNT) D-61
status/interrupt/control
register
(FCSMSIC)
D-59
time base bus drivers 10-6
timing (electricals) A-31
FCSMCNT D-61
FCSMSIC D-59
FE 9-28, D-46
Final sample time 8-13
FLAG D-63, D-68
FORCA D-65
FORCB D-65
Force (FORCA/B) D-65
FORMERR D-94
fPWM 10-16
fQCLK 8-24
FQD 11-12
FQM 11-13
Frame 9-25
size 9-28
Frames
overload 13-16
remote 13-15
Framing error (FE) flag 9-28, D-46
Free-running counter submodule.
See FCSM 10-5
FREEZ ACK 13-16
FREEZE
assertion response (FRZ)
BIUSM 10-3, D-57
QADC 8-7, D-29
336376UMBook Page 5 Friday, November 15, 1996 2:09 PM